An empirical comparison of the Kendall Square Research KSR-1 and Stanford DASH multiprocessors

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An empirical comparison of the Kendall Square Research KSR-1 and Stanford DASH multiprocessors

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Conference on High Performance Networking and Computing archive
Proceedings of the 1993 ACM/IEEE conference on Supercomputing table of contents

Portland, Oregon, United States

Pages: 214 - 225

Year of Publication: 1993

ISBN:0-8186-4340-4

Authors

J. P. Singh	Computer Systems Laboratory, Stanford University
T. Joe	Computer Systems Laboratory, Stanford University
J. L. Hennessy	Computer Systems Laboratory, Stanford University
A. Gupta	Computer Systems Laboratory, Stanford University

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 23, Citation Count: 22

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Anant Agarwal , Beng-Hong Lim , David Kranz , John Kubiatowicz, APRIL: a processor architecture for multiprocessing, Proceedings of the 17th annual international symposium on Computer Architecture, p.104-114, May 28-31, 1990, Seattle, Washington, United States
	2	D. H. Bailey, FFTs in external or hierarchical memory, The Journal of Supercomputing, v.4 n.1, p.23-35, Mar. 1990 [doi>10.1007/BF00162341]
	3	Gordon Bell, Ultracomputers: a teraflop before its time, Communications of the ACM, v.35 n.8, p.26-47, Aug. 1992 [doi>10.1145/135226.135227]
	4	Henry Burkhardt 111 et al. Overview of the KSR1 Computer System. Technical Report KSR-TR- 9202001, Kendall Square Research, Boston, February 1992.
	5	Alan Gottlieb et al. The NYU Ultracomputer - Designing a MIMD, shared memory parallel machine. IEEE Transactions on Computers, 32(2): 175-189, February 1983.
	6	Erik Hagersten, Seif Haridi, and David H.D. Warren. The cache-coherence protocol of the data diffusion machine, in Michel Dubois mad Shreekant Thakkar, editors, Cache and Interconnect Architectures in Mult~processors. Kluwer Academic Publishers, 1990.
	7	Erik Hagersten , Anders Landin , Seif Haridi, DDM: A Cache-Only Memory Architecture, Computer, v.25 n.9, p.44-54, September 1992 [doi>10.1109/2.156381]
	8	Monica D. Lam , Edward E. Rothberg , Michael E. Wolf, The cache performance and optimizations of blocked algorithms, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.63-74, April 08-11, 1991, Santa Clara, California, United States
	9	Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Anoop Gupta , John Hennessy, The directory-based cache coherence protocol for the DASH multiprocessor, Proceedings of the 17th annual international symposium on Computer Architecture, p.148-159, May 28-31, 1990, Seattle, Washington, United States
	10	Edward Rothberg , Jaswinder Pal Singh , Anoop Gupta, Working sets, cache sizes, and node granularity issues for large-scale multiprocessors, Proceedings of the 20th annual international symposium on Computer architecture, p.14-26, May 16-19, 1993, San Diego, California, United States
	11	Jaswinder Pal Singh , John L. Hennessy, Finding and exploiting parallelism in an ocean simulation program: experience, results, and implications, Journal of Parallel and Distributed Computing, v.15 n.1, p.27-48, May 1992 [doi>10.1016/0743-7315(92)90056-S]
	12	Jaswinder Pal Singh , John L. Hennessy , Anoop Gupta, Scaling Parallel Programs for Multiprocessors: Methodology and Examples, Computer, v.26 n.7, p.42-50, July 1993 [doi>10.1109/MC.1993.274941]
	13	Jaswinder Pal Singh et al. "Load balancing and data locality in parallel hierarchial N-body metho&", Technical Report CSL-TR-92-505, Stanford University, February 1992.
	14	Jaswinder Pal Singh , Wolf-Dietrich Weber , Anoop Gupta, SPLASH: Stanford parallel applications for shared-memory, ACM SIGARCH Computer Architecture News, v.20 n.1, p.5-44, March 1992 [doi>10.1145/130823.130824]
	15	Per Stenström , Truman Joe , Anoop Gupta, Comparative performance evaluation of cache-coherent NUMA and COMA architectures, Proceedings of the 19th annual international symposium on Computer architecture, p.80-91, May 19-21, 1992, Queensland, Australia
	16	Joseph Torrellas, Moniea S. Larn, and John L. Hennessy. Shared data placement optimizations to reduce multiprocessor cache miss rates. In Proceedings of the International Conference on Parallel Processing, pages 266-270, 1990. Vol. II.

CITED BY 22

	Eric L. Boyd , Edward S. Davidson, Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments, Proceedings of the 8th international conference on Supercomputing, p.166-175, July 11-15, 1994, Manchester, England
	R. H. Saavedra , R. S. Gaines , M. J. Carlton, Micro benchmark analysis of the KSR1, Proceedings of the 1993 ACM/IEEE conference on Supercomputing, p.202-213, December 1993, Portland, Oregon, United States
	Dongming Jiang , Jaswinder Pal Singh, Scaling application performance on a cache-coherent multiprocessor, ACM SIGARCH Computer Architecture News, v.27 n.2, p.305-316, May 1999
	Dongming Jiang , Hongzhang Shan , Jaswinder Pal Singh, Application restructuring and performance portability on shared virtual memory and hardware-coherent multiprocessors, ACM SIGPLAN Notices, v.32 n.7, p.217-229, July 1997
	Dongming Jiang , Jaswinder Pal Singh, A methodology and an evaluation of the SGI Origin2000, ACM SIGMETRICS Performance Evaluation Review, v.26 n.1, p.171-181, June 1998
	Remzi H. Arpaci , David E. Culler , Arvind Krishnamurthy , Steve G. Steinberg , Katherine Yelick, Empirical evaluation of the CRAY-T3D: a compiler perspective, ACM SIGARCH Computer Architecture News, v.23 n.2, p.320-331, May 1995
	Dongming Jiang , Brian O'Kelley , Xiang Yu , Sanjeev Kumar , Angelos Bilas , Jaswinder Pal Singh, Application scaling under shared virtual memory on a cluster of SMPs, Proceedings of the 13th international conference on Supercomputing, p.165-174, June 20-25, 1999, Rhodes, Greece
	Jennifer M. Anderson , Saman P. Amarasinghe , Monica S. Lam, Data and computation transformations for multiprocessors, ACM SIGPLAN Notices, v.30 n.8, p.166-178, Aug. 1995
	Siddhartha Chatterjee , Alvin R. Lebeck , Praveen K. Patnala , Mithuna Thottethodi, Recursive array layouts and fast parallel matrix multiplication, Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures, p.222-231, June 27-30, 1999, Saint Malo, France
	Mark Heinrich , Vijayaraghavan Soundararajan , John Hennessy , Anoop Gupta, A Quantitative Analysis of the Performance and Scalability of Distributed Shared Memory Cache Coherence Protocols, IEEE Transactions on Computers, v.48 n.2, p.205-217, February 1999
	J. P. Singh , C. Holt , J. L. Hennessy , A. Gupta, A parallel adaptive fast multipole method, Proceedings of the 1993 ACM/IEEE conference on Supercomputing, p.54-65, December 1993, Portland, Oregon, United States
	Chau-Wen Tseng , Jennifer M. Anderson , Saman P. Amarasinghe , Monica S. Lam, Unified compilation techniques for shared and distributed address space machines, Proceedings of the 9th international conference on Supercomputing, p.67-76, July 03-07, 1995, Barcelona, Spain
	C. R. M. Sundaram , Derek L. Eager, Future applicability of bus-based shared memory multiprocessors, Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures, p.203-212, June 24-26, 1995, Santa Barbara, California, United States
	Siddhartha Chatterjee , Vibhor V. Jain , Alvin R. Lebeck , Shyam Mundhra , Mithuna Thottethodi, Nonlinear array layouts for hierarchical memory systems, Proceedings of the 13th international conference on Supercomputing, p.444-453, June 20-25, 1999, Rhodes, Greece
	Siddhartha Chatterjee , Alvin R. Lebeck , Praveen K. Patnala , Mithuna Thottethodi, Recursive Array Layouts and Fast Matrix Multiplication, IEEE Transactions on Parallel and Distributed Systems, v.13 n.11, p.1105-1123, November 2002
	Steven K. Reinhardt , James R. Larus , David A. Wood, Tempest and typhoon: user-level shared memory, 25 years of the international symposia on Computer architecture (selected papers), p.497-508, June 27-July 02, 1998, Barcelona, Spain
	S. K. Reinhardt , J. R. Larus , D. A. Wood, Tempest and typhoon: user-level shared memory, ACM SIGARCH Computer Architecture News, v.22 n.2, p.325-336, April 1994
	Xiaodong Zhang , Yong Yan, Comparative Modeling and Evaluation of CC-NUMA and COMA on Hierarchical Ring Architectures, IEEE Transactions on Parallel and Distributed Systems, v.6 n.12, p.1316-1331, December 1995
	Aleksandra Grujíc , Milo Tomasevíc , Veljko Milutinovíc, A Simulation Study of Hardware-Oriented DSM Approaches, IEEE Parallel & Distributed Technology: Systems & Technology, v.4 n.1, p.74-83, March 1996
	Babak Falsafi , David A. Wood, Cost/performance of a parallel computer simulator, ACM SIGSIM Simulation Digest, v.24 n.1, p.173-182, July 1994
	James R. Larus, Compiling for shared-memory and message-passing computers, ACM Letters on Programming Languages and Systems (LOPLAS), v.2 n.1-4, p.165-180, March–Dec. 1993
	Randy Wright , Arun Kumar, HP scalable computing architecture, Proceedings of the 1st conference on Industrial Experiences with Systems Software, p.3-3, October 22, 2000, San Diego, California