Wisconsin Architectural Research Tool Set

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Wisconsin Architectural Research Tool Set

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ACM SIGARCH Computer Architecture News archive
Volume 21 , Issue 4 (September 1993) table of contents

Pages: 8 - 10

Year of Publication: 1993

ISSN:0163-5964

Authors

Mark D. Hill
James R. Larus
Alvin R. Lebeck
Madhusudhan Talluri
David A. Wood

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 9, Citation Count: 10

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Thomas Ball , James R. Larus, Optimally profiling and tracing programs, Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.59-70, January 19-22, 1992, Albuquerque, New Mexico, United States [doi>10.1145/143165.143180]
	2	J. R. Larus, Abstract execution: a technique for efficiently tracing programs, Software—Practice & Experience, v.20 n.12, p.1241-1258, Dec. 1990 [doi>10.1002/spe.4380201205]
	3	Computer Staff, Efficient program tracing, Computer, v.26 n.5, p.52-61, May 1993 [doi>10.1109/2.211900]
	4	[1] Alvin R. Lebeck and David A. Wood, "Cache Profiling and the SPEC Benchmarks: A Case Study," Technical Report, University of Wisconsin, March 1992.
	5	M. D. Hill , A. J. Smith, Evaluating Associativity in CPU Caches, IEEE Transactions on Computers, v.38 n.12, p.1612-1630, December 1989 [doi>10.1109/12.40842]
	6	Jeffrey D. Gee , Mark D. Hill , Dionisios N. Pnevmatikatos , Alan Jay Smith, Cache Performance of the SPEC92 Benchmark Suite, IEEE Micro, v.13 n.4, p.17-27, July 1993 [doi>10.1109/40.229711]
	7	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996

CITED BY 10

	Siddhartha Chatterjee , Erin Parker , Philip J. Hanlon , Alvin R. Lebeck, Exact analysis of the cache behavior of nested loops, ACM SIGPLAN Notices, v.36 n.5, p.286-297, May 2001
	Doug Burger , James R. Goodman , Alain Kägi, Memory bandwidth limitations of future microprocessors, ACM SIGARCH Computer Architecture News, v.24 n.2, p.78-89, May 1996
	Vasily G. Moshnyaga, Reducing cache engery through dual voltage supply, Proceedings of the 2001 conference on Asia South Pacific design automation, p.302-305, January 2001, Yokohama, Japan
	W. Ye , N. Vijaykrishnan , M. Kandemir , M. J. Irwin, The design and use of simplepower: a cycle-accurate energy estimation tool, Proceedings of the 37th conference on Design automation, p.340-345, June 05-09, 2000, Los Angeles, California, United States
	P. Pereira , L. Heutte , Y. Lecourtier, Source-to-Source Instrumentation for the Optimization of an Automatic Reading System, The Journal of Supercomputing, v.18 n.1, p.89-104, Jan. 2001
	Woo-Chan Park , Kil-Whan Lee , Il-San Kim , Tack-Don Han , Sung-Bong Yang, An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors, IEEE Transactions on Computers, v.52 n.11, p.1501-1508, November 2003
	Woo-Chan Park , Cheong-Ghil Kim , Duk-Ki Yoon , Kil-Whan Lee , Il-San Kim , Tack-Don Han, A consistency-free memory architecture for sort-last parallel rendering processors, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.5-6, p.272-284, May, 2007
	Moon-Hee Choi , Woo-Chan Park , Francis Neelamkavil , Tack-Don Han , Shin-Dug Kim, An Effective Visibility Culling Method Based on Cache Block, IEEE Transactions on Computers, v.55 n.8, p.1024-1032, August 2006
	Greg Stitt , Frank Vahid, Binary synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-30, August 2007
	Greg Stitt , Frank Vahid, Thread warping: a framework for dynamic synthesis of thread accelerators, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria