Flexible cache error protection using an ECC FIFO

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Flexible cache error protection using an ECC FIFO

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Conference on High Performance Networking and Computing archive
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis table of contents

Portland, Oregon

SESSION: Technical papers table of contents

Article No.: 49

Year of Publication: 2009

ISBN:978-1-60558-744-8

Authors

Doe Hyun Yoon	The University of Texas at Austin
Mattan Erez	The University of Texas at Austin

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
: IEEE CS

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 19, Downloads (12 Months): 61, Citation Count: 0

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ABSTRACT

We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of adding redundant ECC information to each cache line, our ECC FIFO mechanism off-loads the extra information to off-chip DRAM. We augment each cache line with a tier-1 code, which provides error detection consuming limited resources. The redundancy required for strong protection is provided by a tier-2 code placed in off-chip memory. Because errors that require tier-2 correction are rare, the overhead of accessing DRAM is unimportant. We show how this method can save 15--25% and 10--17% of on-chip cache area and power respectively while minimally impacting performance, which decreases by 1% on average across a range of scientific and consumer benchmarks.

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