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Vector prefix addition on sub-bus mesh computers
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Source ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures table of contents
Velen, Germany
Pages: 387 - 396  
Year of Publication: 1993
ISBN:0-89791-599-2
Authors
Sponsors
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture
European Comp Soc : European Computer Society
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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T. Blank. The MasPar MP-I architecture. Proceedings of COMPCON Spring 90- The Thirty-Fifth IEEE Computer Society International Conference. pp. 20-24, 1990.
 
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C.M. Fiduccia, R.M. Mattheyses, and R.E. Stearns. Efficient scan operators for bit-serial processor arrays. Proceedings of 2rid Symposium on the Frontiers of Massively Parallel Computation. pp. 105-111, 1988.
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Q.F. Stout. Meshes with multiple buses. 27th Annual IEEE Symposium on Foundations of Computer Science. pp. 264-273, 1986.

Collaborative Colleagues:
Richard E. Ladner: colleagues
Jordan Lampe: colleagues
Richard Rogers: colleagues