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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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M. Ajtai, N. Alon, J. Bruck, R. Cypher, C.T. Ho, M. Noar and E. Szemerddi, Fault Tolerant Graphs, Perfect Hash Functions and Disjoint Paths, Proc. of 33rd Annual IEEE Syrup. on Foundations of Computer Science, pp. 693-702, 1992.
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K. E. Butcher, Design of a Massively Parallel Processor, IEEE Trans. on Computers, vol. C-29, no. 9, pp. 836- 840, September 1980.
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C. Berge, Graphs, page 218, a Theorem attributed to Moon, North-Holland, 1985.
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J. Bruck, R. Cypher and C.-T. Ho, Fault-Tolerant Meshes with Minimal Numbers of Spares, Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, pp. 288-295, Dallas TX, December 1991.
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J. Bruck, R. Cypher and C.-T. Ho, Efficient Fault- Tolerant Mesh and Hypercubes Architectures, Proceedings of the 1992 International Symposium on Fanlt- Tolerant Computing, pp. 162-169.
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3. Bruck, R. Cypher and C.-T. Ho, Fault-Tolerant de Bruijn and Shuffle-Ezchange Networks, Proceedings of the 1992 International Conference on Parallel Processing, pp. 46-50, Vol. IiI, St. Charles, IL, August 1992.
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J. Bruck, R. Cypher and C.-T. Ho, Tolerating Faults in a Mesh with a Row of Spare Nodes, Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing, pp. 12-19, Dallas TX, December 1992.
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S. Dutt and :I. P. Hayes, Some Practical issues in the Design of Fault-Tolerant Multiprocessors, Proceedings of the 21st International Symposium on Fault-Tolerant Computing, pp. 292-299, June 1991.
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J. P. Hayes, A Graph Model for Fault-Tolerant Computing Systems, IEEE Trans. on Computers, vol. C-25, no. 9, pp. 875-884, September 1976.
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C. Kaklamanis, A. R. Karlin, F. T. Leighton, V. Milenkovic, P. Raghavan, S. Rao, C. Thomborson and A. Tsantilaz, A symptoticall!t Tight Bounds for Computing with Faulty Arrays of Processors, Proc. of 31st Annum IEEE Syrup. on Foundations of Computer Science, pp. 285-296, October 1990.
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S.-Y. Kuo and W. K. Fuchs, E#cient Spare Allocation for Reconfigurable Arrays, IEEE Design and Test, pp. 24-31, February 1987.
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T. Leighton and C. E. Leiserson, Wafer Scale integra. tion of S#/stolic Arra#ts, IEEE Trans. on Computers, vol. C-34, no. 5, pp. 448--461, May 1985.
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T. Leighton, B. Ma#gs #nd R. Sitar#man, On the Fault Tolerance o} Some Popular Bounded.Degree Networks, Proc. of 33rd Annum IEEE Syrup. on Foundations of Computer Science, pp. 542-552, 1992.
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M. Paoli, W. W. Wong and C. K. Wong, Minimum k- Hamiltonian Graphs, II, J. of Graph Theory, Vol. 10, pp. 79-95, 1986.
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A. L. Rosenberg, The Diogenes Approach to Testable Fault. Tolerant VLSI Processor Arrays, IEEE Trans. on Computers, Vol. C-32, no. 10, pp. 902-910, October 1983.
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W. W. Wong and C. K. Woag, Minimum k- Hamiltonian Graphs, :1. of Graph Theory, Vol. 8, pp. 155-165, 1984.
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CITED BY 5
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Richard Cole , Bruce Maggs , Ramesh Sitaraman, Multi-scale self-simulation: a technique for reconfiguring arrays with faults, Proceedings of the twenty-fifth annual ACM symposium on Theory of computing, p.561-572, May 16-18, 1993, San Diego, California, United States
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