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The J-machine multicomputer: an architectural evaluation
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Source International Symposium on Computer Architecture archive
Proceedings of the 20th annual international symposium on Computer architecture table of contents
San Diego, California, United States
Pages: 224 - 235  
Year of Publication: 1993
ISBN:0-8186-3810-9
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Authors
Sponsors
IEEE-CS : Computer Society
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 8,   Downloads (12 Months): 41,   Citation Count: 68
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ABSTRACT

The MIT J-Machine multicomputer has been constructed to study the role of a set of primitive mechanisms in providing efficient support for parallel computing. Each J-Machine node consists of an integrated multicomputer component, the Message-Driven Processor (MDP), and 1 MByte of DRAM. The MDP provides mechanisms to support efficient communication, synchronization, and naming. A 512 node J-Machine is operational and is due to be expanded to 1024 nodes in March 1993. In this paper we discuss the design of the J-Machine and evaluate the effectiveness of the mechanisms incorporated into the MDP. We measure the performance of the communication and synchronization mechanisms directly and investigate the behavior of four complete applications.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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CITED BY  68

Collaborative Colleagues:
Michael D. Noakes: colleagues
Deborah A. Wallach: colleagues
William J. Dally: colleagues