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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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J. A. Abraham and D. D. Gajski. Design of testable structure defined by simple loops. IEEE Trans. on Computers, C-30, 1981.
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D. Bhattacharya and J. P. Hayes. Fast and easily testable implementation of arithmetic functions. Proceedings of the 16th International Symposium on Fault Tolerant Computing Systems, July 1986.
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R. Fritzemeier, J. Soden, R. K. Treece, and C. Hawkins. Increased CMOS IC stuck-at fault coverage with reduced IDDQ test sets. Proceedings of ITC. pp427-435, 1990.
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J. P. Hayes, On realizations of boolean functions requiring a minimal or near-minimal number of tests, IEEE Trans. on Computers C-20, pp1506- 1513, 1971.
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G. Markowsky. A straightforward technique for producing minimal multiple fault test sets for fanout-free combinational circuits. Technical Report RC 6222, IBM T. J. Watson Research Center, Yorktown Heights, 1976.
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S.C. Seth, and K.L. Kodandapani. Diagnosis of faults in linear tree networks. IEEE Trans. on Computers, C-26(1), pp29-33, :}an. 1977.
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H. Wu, U. Sparmann, "On the Assignment Complexity of VLSI Tree Systems", Proceeding of The Seventh International Symposium on Computer and Information Sciences, pp97-103, 1992.
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H. Wu, "On the Test Complexity of Tree VLSI Systems", Technical Report, SFB 124-B1, 08/1992, FB-Informatik, Universit~t des Saarlandes, Germany.
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