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ABSTRACT

Efficient hardware architectures for the Luffa hash algorithm are proposed in this work. We explore different tradeoffs and propose several architectures, targeting both compact and high-throughput designs. Implemented using UMC 0.13 μm CMOS standard cell library, the most compact architecture of Luffa-224/256 contains 18,260 GE. The same version, optimized for speed, achieves a throughput of almost 32 Gbps, while the throughput of the pipelined design approaches 291.7 Gbps. Concerning the final throughput, our implementations outperform state of the art implementations of the existing hash standards.

REFERENCES

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INDEX TERMS

Primary Classification:
  E. Data
  E.2 DATA STORAGE REPRESENTATIONS
      Subjects: Hash-table representations

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance, Security

Keywords:
Luffa hash algorithm, ASIC implementations, SHA-3 competition