Register allocation for high-level synthesis using dual supply voltages

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Register allocation for high-level synthesis using dual supply voltages

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents

San Francisco, California

SESSION: Heuristic approaches to hardware optimization table of contents

Pages 937-942

Year of Publication: 2009

ISBN:978-1-60558-497-3

Authors

Insup Shin	KAIST, Daejeon, Korea
Seungwhun Paik	KAIST, Daejeon, Korea
Youngsoo Shin	KAIST, Daejeon, Korea

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 12, Downloads (12 Months): 13, Citation Count: 0

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ABSTRACT

Reducing the power consumption of memory elements is known to be the most influential in minimizing total power consumption, since designs tend to use more memories these days. In this paper, we address a problem of high-level synthesis with the objective of minimizing power consumption of storage using dual-V_dd. Specifically, we propose a complete design framework that starts from dual-V_dd scheduling, dual-V_dd allocation, and controller synthesis down to the final layout. Its main feature is dual-V_dd register allocation, which exploits timing slacks left in the data-path after operation scheduling. In experiments on benchmark designs implemented in 1.08 V (with V_ddl of 0.8 V), 65-nm CMOS technology, both switching and leakage power were reduced by 20% on average, respectively, compared to data-path with dual-V_dd applied to functional units alone. Detailed analysis of slack histogram, area, wirelength, and congestion were performed to assess feasibility of the design framework.

REFERENCES

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