| Internet-in-a-Box: emulating datacenter network architectures using FPGAs |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 46th Annual Design Automation Conference
table of contents
San Francisco, California
SESSION: Technologies for green data centers
table of contents
Pages 880-883
Year of Publication: 2009
ISBN:978-1-60558-497-3
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Downloads (6 Weeks): 13, Downloads (12 Months): 13, Citation Count: 0
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ABSTRACT
In this paper we describe the Internet-in-a-Box datacenter network emulator, an FPGA-based tool for researchers to rapidly experiment with O(10,000) node datacenter network architectures. Our basic approach to emulation involves constructing a model of the target architecture by composing simplified hardware models of key datacenter building blocks, including switches, routers, links, and servers. Since models in our system are implemented in programmable hardware, designers have full control over emulated buffer sizes, line rates, topologies, and many other network properties. Full system control also gives researchers a significant degree of system visibility. Additionally, because our node model emulates servers using a full SPARC v8 ISA compatible processor, each node in the network is capable of running real applications. This allows researchers to study a network under complex real-world workloads at a scale that matches that of a large datacenter today. Moreover, because the system is a private testbed, experiments can be deterministic and therefore reproduced by other researchers. Lastly, the system is cost effective for designers, and we show that using FPGA technology on the market today we can actually emulate a network of 256-nodes for about $2,000.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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R. H. Katz, "Tech Titans Building Boom: The Architecture of Internet Datacenters," IEEE Spectrum, February 2009
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Zhangxi Tan, Krste Asanović, and David A. Patterson, "An FPGA Host-Multithreaded Functional Model for SPARC v8", 3rd Workshop on Architectural Research Prototyping, at 35th International Symposium on Computer Architecture, June 2008.
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Digilent Virtex-5 OpenSPARC Evaluation Platform, http://www.digilentinc.com/Products/Detail.cfm?NavTop=2&NavSub=599&Prod=XUPV5
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E. Krevat, V. Vasudevan, A. Phanishayee, D. Andersen, G. Ganger, G. Gibson, S. Seshan. On Application-level Approaches to Avoiding TCP Throughput Collapse in Cluster-Based Storage Systems. Proceedings of the 2nd international Petascale Data Storage Workshop held in conjunction with Supercomputing '07. November 11, 200
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