Transmuting coprocessors: dynamic loading of FPGA coprocessors

ABSTRACT

Field-programmable gates arrays (FPGAs) are increasingly used in general-purpose computing platforms to augment microprocessors, enabling runtime loading of coprocessors customized to speed up some applications. Such transmuting coprocessors create new dynamic management problems involving decisions as to when to load a coprocessor, where to place the coprocessor in the FPGA, or which resident coprocessor to replace. We define a transmuting coprocessor problem based on Intel's FSB-FPGA architecture, with attention on communication and memory contention. We develop an online algorithm to manage coprocessor loading, the AG algorithm, which uses aggregated gains to guide coprocessor load, placement, replacement, and wait decisions. Experiments using embedded system applications, for random, biased, and periodic input application sequences, a range of reconfiguration times, and different FPGA types with different numbers of partial reconfigurable regions, demonstrate that the AG algorithm is robust across a variety of situations. The AG algorithm results are within 15% of an unlimited-size FPGA on average, exhibit a small standard deviation, and show a 1.4x speedup versus a static coprocessor loading approach and a 3x speedup over execution on a microprocessor-only solution.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles

General Terms:
Algorithms, Design, Performance

Keywords:
FPGAs, acceleration, coprocessing, dynamic optimization, online algorithms, runtime configuration