Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization

ABSTRACT

This work addresses the problem of minimizing power/ground noise in the clock tree synthesis. Contrary to the previous approaches which only make use of assigning polarities to clock buffers to reduce power/ground noise, our approach solves a new problem of simultaneous consideration of assigning polarities to clock buffers and determining buffer sizes to fully exploit the effects of buffer sizing together with polarity assignment on the minimization of power/ground noise while satisfying the clock skew constraint. Through experiments with MCNC benchmark circuits, it is shown that the proposed solution produces designs with 19.1% less power and 16.2% less ground noise as well as 15.6% less total peak current over that by the conventional method.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Design, Reliability

Keywords:
buffer insertion, clock synthesis, power/ground noise