Variational capacitance extraction of on-chip interconnects based on continuous surface model

ABSTRACT

In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increasing the number of variables. Based on it, efficient techniques are presented for chip-level capacitance extraction considering the window technique. The sparse-grid-based Hermite polynomial chaos combined with a novel weighted principle factor analysis is employed for intra-window extraction. Then, the inter-window capacitance covariance is calculated through matrix pseudo inverse. Numerical results validate the accuracy and efficiency of the proposed method, which is more than 50 times faster than the Monte-Carlo simulation with 10000 samples.

REFERENCES

• 1: J. Xiong, V. Zolotov and L. He, "Robust extraction of spatial correlation," IEEE Trans. CAD, vol. 26, pp. 619--631, 2007.
• 2: X. Qi, A. Gyure, Y. Luo, S. C. Lo, M. Shahram, and K. Singhal, "Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies," in Proc. GLS-VLSI, pp. 14--18, 2006
• 3: Z. Zhu, A. Demir, and J. White, "A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance," in Proc. ICCAD, pp. 887--891, 2004
• 4: Z. Zhu and J. White, "Fastsies: A fast stochastic integral equation solver for modeling the rough surface effect," in Proc. ICCAD, pp. 675--682, 2005.
• 5: R. Jiang, W. Fu, J. M. Wang, V. Lin, and C. C.-P. Chen, "Efficient statistical capacitance variability modeling with orthogonal principle factor analysis," in Proc. ICCAD, pp. 683--690, 2005.
• 6: H. Zhu, X. Zeng, W. Cai, J. Xue, and D. Zhou, "A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology," in Proc. DATE, pp. 1514--1519, 2007.
• 7: J. Cui, G. Chen, R. Shen, S. X.-D. Tan, W. Yu, and J. Tong, "Variational capacitance modeling using orthogonal polynomial method," in Proc. GLS-VLSI, pp. 23--28, 2008
• 8: T. El-Moselhy and L. Daniel, "Stochastic integral equation solver for efficient variation-aware interconnect extraction," in Proc. DAC, pp. 415--420, June 2008.
• 9: W. Zhang, W. Yu, Z. Wang, Z. Yu, R. Jiang, and J. Xiong, "An efficient method for chip-level statistical capacitance extraction considering process variations with spatial correlation," in Proc. DATE, pp. 580--585, Mar. 2008.
• 10: A. Singhee, S. Singhal, and R. A. Rutenbar, "Practical, fast Monte Carlo statistical static timing analysis: Why and how," in Proc. ICCAD, pp. 190--195, Nov. 2008.
• 11: R. G. Ghanem and P. D. Spanos, Stochastic Finite Elements: A Spectral Approach, New York: Springer-Verlag, 1991.
• 12: D. Xiu and G. E. Karniadakis, "The Wiener-Askey polynomial chaos for stochastic differential equations," in SIAM J. Sci. Comput., vol. 24, no. 2, pp. 619--644, Oct. 2002.
• 13: E. Novak and K. Ritter, "Simple cubature formulas with high polynomial exactness," Constructive Approximation, vol. 15, no. 4, pp. 449--522, Dec. 1999.
• 14: K. Nabors and J. White, "FastCap: A multipole accelerated 3-D capacitance extraction program,", IEEE Trans. CAD, vol. 10, pp. 1447--1459, Nov. 1991.
• 15: W. Shi and F. Yu, "A divide-and-conquer algorithm for 3-D capacitance extraction," IEEE Trans. CAD, vol. 23, no. 8, pp. 1157--1163, Aug. 2004.
• 16: A. Mitev, M. Marefat, D. Ma, and J. M. Wang, "Principle Hessian direction based parameter reduction with process variation," in Proc. ICCAD, pp. 632--637, Nov. 2007.

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING

Additional Classification:
  I. Computing Methodologies
  I.6 SIMULATION AND MODELING

General Terms:
Algorithms, Design, Theory

Keywords:
geometric variation modeling, hermite polynomial chaos method, quadratic variation model, spatial correlation, variational capacitance extraction