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Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents
San Francisco, California
SESSION: Challenges of memory-aware design for embedded systems table of contents
Pages 744-749  
Year of Publication: 2009
ISBN:978-1-60558-497-3
Authors
José A. Baiocchi  University of Pittsburgh, Pittsburgh, PA
Bruce R. Childers  University of Pittsburgh, Pittsburgh, PA
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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ABSTRACT

Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-purpose systems, embedded systems often have specialized memory resources, such as a fast scratchpad memory, that can be used to mitigate DBT performance overhead. This paper presents the Heterogeneous Code Cache (HCC), a code cache split among scratchpad and main memory. We explore several HCC management policies and show that, on average, an HCC outperforms a code cache allocated only to scratchpad or only to main memory.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
K. Adams and O. Agesen. A comparison of software and hardware techniques for x86 virtualization. In International Conference on Architectural Support for Programming Languages and Operating Systems, 2006.
 
2
T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. Computer, 35(2):59--67, 2002.
 
3
J. A. Baiocchi, B. R. Childers, J. W. Davidson, and J. D. Hiser. Reducing pressure in bounded DBT code caches. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, 2008.
 
4
J. A. Baiocchi, B. R. Childers, J. W. Davidson, J. D. Hiser, and J. Misurda. Fragment cache management for dynamic binary translators in embedded systems with scratchpad. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, 2007.
 
5
V. Bala, E. Duesterwald, and S. Banerjia. Dynamo: a transparent dynamic optimization system. In Conference on Programming Language Design and Implementation, 2000.
 
6
R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel. Scratchpad memory: design alternative for cache on-chip memory in embedded systems. In International Conference on Hardware/Software Codesign, 2002.
 
7
D. Bruening and S. Amarasinghe. Maintaining consistency and bounding capacity of software code caches. In International Symposium on Code Generation and Optimization, 2005.
 
8
S. Debray and W. Evans. Profile-guided code compression. In Conference on Programming Language Design and Implementation, 2002.
 
9
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In IEEE Workshop on Workload Characterization, 2001.
 
10
K. Hazelwood and M. D. Smith. Code cache management schemes for dynamic optimizers. In Workshop on Interaction between Compilers and Computer Architectures, 2002.
 
11
K. Hazelwood and M. D. Smith. Managing bounded code caches in dynamic binary optimization systems. ACM Trans. on Architecture and Code Optimization, 3(3):263--294, 2006.
 
12
J. D. Hiser, D. Williams, W. Hu, J. W. Davidson, J. Mars, and B. R. Childers. Evaluating indirect branch handling mechanisms in software dynamic translation systems. In International Symposium on Code Generation and Optimization, 2007.
 
13
J. E. Miller and A. Agarwal. Software-based instruction caching for embedded processors. In International Conference on Architectural Support for Programming Languages and Operating Systems, 2006.
 
14
K. Scott, N. Kumar, S. Velusamy, B. Childers, J. W. Davidson, and M. L. Soffa. Retargetable and reconfigurable software dynamic translation. In International Symposium on Code Generation and Optimization, 2003.