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ABSTRACT

This paper introduces a new unobtrusive and cost-effective method for the capture and compression of program execution traces in real-time, which is based on a double move-to-front transformation. We explore its effectiveness and describe a cost-effective hardware implementation. The proposed trace compressor requires only 0.12 bits per instruction of trace port bandwidth, at the cost of 25K gates.

REFERENCES

• 1: ARM, "Embedded Trace Macrocell Architecture Specification," http://infocenter.arm.com.
• 2: Altera, "Nios II Processor Reference Handbook," http://www.altera.com.
• 3: Xilinx, "MicroBlaze Processor Reference Guide Embedded Development Kit EDK 10.1i," http://www.xilinx.com.
• 4: "Lauterbach GmbH," http://www.lauterbach.com.
• 5: C.-F. Kao, et al., "A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors," IEEE Transactions on Circuits and Systems, vol. 54, pp. 530--543, 2007.
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• 7: Milena Milenkovic , Aleksandar Milenkovic , Martin Burtscher, Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces, Proceedings of the 2007 Data Compression Conference, p.283-292, March 27-29, 2007 [doi>10.1109/DCC.2007.10]
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

Additional Classification:
  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.5 Testing and Debugging

General Terms:
Design, Verification

Keywords:
compression, debugging, program trace