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Fault models for embedded-DRAM macros
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents
San Francisco, California
SESSION: Targeted test and diagnosis table of contents
Pages: 714-719  
Year of Publication: 2009
ISBN:978-1-60558-497-3
Authors
Mango C.-T. Chao  National Chiao-Tung University, Hsinchu, Taiwan
Hao-Yu Yang  National Chiao-Tung University, Hsinchu, Taiwan
Rei-Fu Huang  MediaTek Inc., Hsinchu, Taiwan
Shih-Chin Lin  United Microelectronics Corporation, Hsinchu, Taiwan
Ching-Yu Chin  National Chiao-Tung University, Hsinchu, Taiwan
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Mango C.-T. Chao: colleagues
Hao-Yu Yang: colleagues
Rei-Fu Huang: colleagues
Shih-Chin Lin: colleagues
Ching-Yu Chin: colleagues