Process variation characterization of chip-level multiprocessors

ABSTRACT

Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem via conservative assumptions is sub-optimal. Instead, operating systems may adapt task assignment and power management decisions to the variable characteristics of cores, improving system-wide power consumption and performance. Researchers have proposed such adaptation techniques. However, they rely on knowledge of CMP process variation (PV) maps. These maps are not provided by processor vendors, providing them would impose additional cost during the testing process, and static maps would not permit adaptation to aging effects. Further progress on developing and validating PV aware control techniques for CMPs requires access to PV maps for real processors. We present an online technique to extract the PV maps of CMPs. Potentially automatic temperature measurements with built-in on-die sensors during the execution of characterization workloads are used to determine variation in leakage power consumption. The proposed technique is applied to real CMPs, and the resulting PV maps are used within a PV aware task assignment and scheduling algorithm.

REFERENCES

• 1: S. Borkar, et al., "Parameter variation and impact on circuits and microarchitecture," in Proc. Design Automation Conf., June 2003, pp. 338--342.
• 2: R. Teodorescu and J. Torrellas, "Variation-aware application scheduling and power management for chip multiprocessors," in Proc. Int. Symp. Computer Architecture, June 2008.
• 3: P. Ndai, et al., "Within-die variation-aware scheduling in superscalar processors for improved throughput," in IEEE Trans. Computers, vol. 57, no. 7, July 2008.
• 4: J. Fourier, The Analytical Theory of Heat, 1822.
• 5: "BSIM4," http://www-device.eecs.berkeley.edu/~bsim4/bsim4.html.
• 6: Z. Chen, et al., "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," in Proc. Int. Symp. Low Power Electronics & Design, Aug. 1998, pp. 239--244.
• 7: C. Poirier, et al., "Power and temperature control on a 90 nm Itanium--family processor," in Proc. Int. Solid-State Circuits Conf., Feb. 2005, pp. 304--305.
• 8: "Core 2 Quad and Duo temperature guide," http://www.tomshardware.com/forum/221745-29-core-quad-temperature-guide.
• 9: A. Keshavarzi, "Technology scaling and low-power circuit design," in The VLSI Handbook, W.-K. Chen, Ed. CRC Press, 2007, ch. 21, p. 21.12.
• 10: "CPLEX," ILOG, Inc., http://www.ilog.com/products/cplex.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Design, Performance, Verification

Keywords:
characterization, process variation, software