A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors

ABSTRACT

We present a voltage-scalable and process-variation resilient memory architecture, suitable for MPEG-4 video processors such that power dissipation can be traded for graceful degradation in "quality". The key innovation in our proposed work is a hybrid memory array, which is mixture of conventional 6T and 8T SRAM bit-cells. The fundamental premise of our approach lies in the fact that human visual system (HVS) is mostly sensitive to higher order bits of luminance pixels in video data. We implemented a preferential storage policy in which the higher order luma bits are stored in robust 8T bit-cells while the lower order bits are stored in conventional 6T bit-cells. This facilitates aggressive scaling of supply voltage in memory as the important luma bits, stored in 8T bit-cells, remain relatively unaffected by voltage scaling. The not-so-important lower order luma bits, stored in 6T bit-cells, if affected, contribute insignificantly to the overall degradation in output video quality. Simulation results show average power savings of up to 56%, in the hybrid memory array compared to the conventional 6T SRAM array implemented in 65nm CMOS. The area overhead and maximum output quality degradation (PSNR) incurred were 11.5% and 0.56 dB, respectively.

REFERENCES

• 1: http://www.mpeg4.org
• 2: P. Kuhn, "Algorithms, Complexity Analysis and VLSI architectures for MPEG-4 Motion Estimation", Kluwer Academic Publishers, 1999.
• 3: C. Lin et. al. "A 5mW MPEG4 SP Encoder with 2D Bandwidth-Sharing Motion Estimation for Mobile Application", ISSCC Dig. Tech. Papers, Feb., 2006
• 4: G. V. Varatkar, N. Shanbhag. "Variation-Tolerant Motion Estimation Architecture", IWSPS, 2007
• 5: L. Chang et al., "An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches", IEEE Journal of Solid State Circuits, Vol. 44, No. 4, pp. 956--963, 2008
• 6: I. J. Chang et al., "Fast and Accurate Estimation of Nano-Scaled SRAM Read Failure Probability using Critical Point Sampling", Custom Integrated Circuit Conference (CICC), pp 439--442, Sep. 2005
• 7: K. Takeda et al., "Redefinition of write margin for next-generation SRAM and write-margin monitoring circuit", ISSCC Dig. Tech. Papers, pp. 630--631, Feb. 2006
• 8: Y. Lin et al., "A 242mW 10mm² 1080p H.264/AVC High-Profile Encoder Chip", ISSCC Dig. Tech. Papers, Feb. 2008
• 9: T. Liu et al., "A 125 μW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile applications", IEEE Journal of Solid State Circuits, Vol. 42, No. 1, pp. 161--169, 2007
• 10: V. Bhaskaran, K. Konstantinides, "Image and Video Compression Standards", Kluwer Academic Publishers, Second Edition, 1997
• 11: I. J. Chang et. al, "A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS", ISSCC Dig. Tech. Papers, pp. 388--389, Feb. 2008
• 12: S. Mukhopadhyay, H. Mahmoodi, K. Roy, "Statistical design and optimization of SRAM cell for yield enhancement", IEEE/ACM International Conference on Computer Aided Design, pp. 10--13, 2004

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories

General Terms:
Design

Keywords:
graceful degradation, low power SRAM, supply voltage over-scaling