Debugging from high level down to gate level

ABSTRACT

C-based hardware designs are now accepted as means to increase design productivity. Starting with rather algorithmic design descriptions, incremental refinements are applied to generate high-level synhesizable descriptions which are further processed by high-level and logic synthesis tools. C-based system level design descriptions, such as in SpecC [?] and SystemC [?], can give concise and global views on the behaviors of the designs as well as structures, and various types of dependencies, such as control, data, concurrency, and others, can be extracted quickly. These dependencies can be the bases for efficient and effective debugging for all levels of design descriptions. In this paper, graph representations for various dependencies which are extracted from C-based descriptions are introduced. Then techniques on their uses for debugging in various design levels are discussed. We present static and dynamic tracing methods for dependence analysis as well as techniques that try to establish mapping between implementations and C-based design descriptions.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Verification

Keywords:
dependence analysis, equivalence checking, high-level design, post-silicon debug, system level design