Guess, solder, measure, repeat: how do I get my mixed-signal chip right?

ABSTRACT

Over the past 20 years, EDA has developed a solid digital implementation methodology that combines some restrictions on the design style with a set of comprehensive tools leading to predictable design flows. The recent increased use of analog components in complex SOC designs triggered a set of verification challenges ranging from simple connectivity problems to complex interferences between analog and digital data blocks. This panel discusses the state of the affairs in analog-mixed signal verification and draws a picture of future directions in terms of new approaches and tools.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design, Performance, Verification

Keywords:
SPICE, VHDL, Verilog, Verilog-AMS, analog behavioral modeling, functional verification, low power verification, mixed-signal verification, performance verification