SRAM parametric failure analysis

ABSTRACT

With aggressive technology scaling, SRAM design has been seriously challenged by the difficulties in analyzing rare failure events. In this paper we propose to create statistical performance models with accuracy sufficient to facilitate probability extraction for SRAM parametric failures. A piecewise modeling technique is first proposed to capture the performance metrics over the large variation space. A controlled sampling scheme and a nested Monte Carlo analysis method are then applied for the failure probability extraction at cell-level and array-level respectively. Our 65nm SRAM example demonstrates that by combining the piecewise model and the fast probability extraction methods, we have significantly accelerated the SRAM failure analysis.

REFERENCES

• 1: B. H. Calhoun, et al., "Digital circuit design challenges and opportunities in the era of nanoscale CMOS," Proceedings of the IEEE, vol. 96, no. 2, pp. 343--365, Feb. 2008.
• 2: T. Mizuno, J. Okamura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's," IEEE Trans. on Electron Devices, vol. 41, no. 11, pp. 2216--2221, Nov. 1994.
• 3: A. J. Bhavanagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE JSSC, vol. 36, no. 4, pp. 658--665, Apr. 2001.
• 4: R. Heald, and P. Wang, "Variability in sub-100nm SRAM designs," Proc. of ICCAD '04, pp. 347--352, 2004.
• 5: I. M. Sobol, A Primer for the Monte Carlo Method. CRC, Boca Raton, FL, 1994.
• 6: R. Kanj, R. Joshi, and S. Nassif, "Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events," Proc. of DAC '06, pp. 69--72, 2006.
• 7: A. Singhee, and R. A. Rutenbar, "From finance to flip flops: a study of fast quasi-Monte Carlo methods from computational finance applied to statistical circuit analysis," Proc. of ISQED '07, pp. 685--692, 2007.
• 8: R. L. Iman, J. C. Helton, and J. E. Campbell, "An approach to sensitivity analysis of computer models," Journal of Quality Technology, vol. 13, no. 3, pp. 174--183, Jul. 1981.
• 9: C. Wann, et al., "SRAM cell design for stability methodology," Proc. of IEEE VLSI-TSA '05, pp. 21--22, 2005.
• 10: K. Agarwal, and S. Nassif, "Statistical analysis of SRAM cell stability," Proc. of DAC '06, pp. 57--62, 2006.
• 11: S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS," IEEE Trans. on CAD, vol. 24, no. 12, pp. 1859--1880, Dec. 2005.
• 12: A. Singhee, and R. A. Rutenbar, "Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application," Proc. of DATE '07, pp. 16--20, 2007.
• 13: K. Takeda, et. al., "Redefinition of write margin for next-generation SRAM and write-margin monitoring circuit," Proc. of ISSCC '06, pp. 2602--2611, 2006.
• 14: T. C. Hesterberg, "Advances in importance sampling," PhD Dissertation, Stanford University, Palo Alto, CA, 1988.
• 15: J. Wang, X. Li, and L. T. Pileggi, "Parameterized macromodeling for analog system-level design exploration," Proc. of DAC '07, pp. 940--943, 2007.
• 16: S. Boyd, and L. Vandenberghe, Convex Optimization. Cambridge University Press, Cambridge, United Kingdom, 2004.
• 17: E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE JSSC, vol. 22, no. 5, pp. 748--754, Oct. 1987.
• 18: J. M. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd ed. Prentice Hall, Englewood Cliffs, NJ, 2003.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Reliability

Keywords:
SRAM, failure probability estimation, parametric failure, response surface model