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On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents
San Francisco, California
SESSION: Thermal optimization table of contents
Pages 490-495  
Year of Publication: 2009
ISBN:978-1-60558-497-3
Authors
Min Bao  IDA, Linkoping University, Linkoping, Sweden
Alexandru Andrei  Ericsson, Linkoping, Sweden
Petru Eles  IDA, Linkoping University, Linkoping, Sweden
Zebo Peng  IDA, Linkoping University, Linkoping, Sweden
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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ABSTRACT

With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy or/and performance optimization will be sufficiently accurate and efficient. In this paper we propose an on-line temperature aware dynamic voltage and frequency scaling (DVFS) technique which is able to exploit both static and dynamic slack. The approach implies an offline temperature aware optimization step and on-line voltage/frequency settings based on temperature sensor readings. Most importantly, the presented approach is aware of the frequency/temperature dependency, by which important additional energy savings are obtained.


REFERENCES

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1
 
2
A. Andrei, P. Eles, Z. Peng, M. Schmitz, and B. M. Al-Hashimi., energy optimization of multiprocessor systems on chip by voltage selection. IEEE Transactions on Very Large Scale Integration Systems, 15((3)):pp. 262--275.
 
3
A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. Al-Hashimi. Quasi-static voltage scaling for energy minimization with time constraints. Design Automation and Test (DATE), April 2005.
 
4
H. Aydin, R. Melhem, D. Moss, and P. Alvarez. Dynamic and aggressive scheduling techniques for power-aware real-time systems. 22nd IEEE Real-Time Systems Symposium (RTSS'01), pages pp. 95--105, Dec. 2001.
 
5
M. Bao, A. Andrei, P. Eles, and Z. Peng. Temperature-aware voltage selection for energy optimization. Design Automation and Test (DATE), April 2008.
 
6
A. P. Chandrakasan and R. W. Brodersen. Low Power Digital CMOS Design. Norwell, MA: Kluwer, 1995.
 
7
R. Cobbold. Temperature effects on mos transistors. Electronic Letters, 2:pp. 190ĺC192, 1966.
 
8
A. Coskun, T. Rosing, and K. Whisnant. Temperature aware task scheduling in mpsocs. Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07, (No. 7):pp. 1--6, April 2007.
 
9
K. Gross, K. Whisnant, and A. Urmanov. Electronic prognostics through continuous system telemetry. In 60th Meeting of the Society for Machine Failure Prevention Technology (MFPT), (1):pp. 53ĺC62, Apr. 2006.
 
10
S. Hsu and A. A. et al. A 4.5-ghz 130-nm 32-kb 10 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE JOURNAL of Solid-State Circuits, May 2003.
 
11
T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on, pages pp. 197--202, Aug. 1998.
 
12
H. Jung, P. Rong, and M. Pedram. Stochastic modeling of a thermally-managed multi-core system. Design Automation Conference, 2008, pages pp. 728--733, June 2008.
 
13
W. Kwon and T. Kim. Optimal voltage allocation techniques for dynamically variable voltage processors. ACM TECS, 4(1):pp. 211--230, 2005.
 
14
Y. Li, B. C. Lee, D. Brooks, Z. Hu, and K. Skadron. Cmp design space exploration subject to physical constraints. HPCA06, pages pp. 15--26, 2006.
 
15
W. P. Liao, L. He, and K. M. Lepak. Temperature and supply voltage aware performance and power modeling at micro-architecture level. IEEE TonCAD, 24(No. 7):pp. 1042ĺC1053, July 2005.
 
16
Y. Liu, H. Yang, R. Dick, H. Wang, and L. Shang. Thermal vs energy optimization for dvfs-enabled processors in embedded systems. Symp. on Quality Electronic Design (ISQED07), (International Symposium on Quality Electronic Design, 2007. ISQED '07. 8th):pp. 204--209, Mar. 2007.
 
17
A. Macii, E. Macii, and M. Poncino. Improving the efficiency of memory partitioning by address clustering. Design, Automation and Test in Europe Conference and Exhibition, 2003.
 
18
S. Martin, K. Flautner, T. Mudge, and D. Blaauw. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors. ICCAD, pages pp. 721--725, 2002.
 
19
S. Murali, A. Mutapcic, and D. A. et al. Temperature control of high-performance multi-core platforms using convex optimization. JOURNAL of VLSI Signal Processing Systems, (Design, Automation and Test in Europe, 2008. DATE '08):pp. 110--115, Mar. 2008.
 
20
B. Razavi. Design of Analog CMOS Integrated Circuits. McGraw-Hill Science Engineering, Erewhon, NC, August 2000.
 
21
K. Sankaranarayanan, S. Velusamy, and K. S. M. R. Stan. A casefor thermal-aware floorplanning at the microarchitectural level. the JOURNAL of Instruction-Level Parallelism, 7:pp. 1--16, Oct 2005.
 
22
M. Sasaki, M. Ikeda, and K. Asada. -1/+0.8°c error, accurate temperature sensor using 90nm 1v cmos for on-line thermal monitoring of vlsi circuits. Microelectronic Test Structures, 2006 IEEE International Conference, pages pp. 9--12, March 2006.
 
23
S. Wang and R. Bettatin. Delay analysis in temp.-constrained hard real-time systems with general task arrivals. RTSS06, pages pp. 323--334, 2006.
 
24
W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. Stan. Hotspot: A compact thermal modeling methodology for early-stage vlsi design. IEEE on VLSI Systems, 14(5):pp. 501--513, May 2006.
 
25
C. Xian, Y.-H. Lu, and Z. Li. Dynamic voltage scaling for multitasking real-time systems with uncertain execution time. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(8):pp. 1467--1478, Aug. 2008.
 
26
Y. Xie and W.-L. Hung. Temperature-aware task allocation and scheduling for embedded multiprocessor systems-on-chip (mpsoc) design. JOURNAL of VLSI Signal Processing Systems, 45(3):pp. 177--189, Dec. 2006.
 
27
Y. Yang and Z. G. et al. Isac: Integrated space and time adaptive chip-package thermal analysis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Jan. 2007.