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ABSTRACT

Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle such conditions accurately at the behavior and register transfer levels, which is problematic since the trend is to move toward high-level synthesis. In this work we propose innovative methods to handle such conditions accurately at high-level designs. In addition, we propose two novel algorithms based on our new methods to minimize the number of registers that need to be initialized at the architecture level, which can reduce the routing resources used by the reset signals and alleviate the routing problem. Our results show that we can identify 53% of the registers that can be uninitialized in a 5-stage pipelined processor within 5 minutes, demonstrating the effectiveness of our approach.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Optimization

General Terms:
Design, Verification

Keywords:
RTL symbolic simulation, don't-care (DC), synthesis