New spare cell design for IR drop minimization in Engineering Change Order

ABSTRACT

Unused spare cells occur inevitably in traditional ECO design flow. It results in inefficient area usage, more leakage, and more IR drop impacts. To tackle these problems, a reconfigurable cell is proposed which serves the dual purposes of decoupling capacitance and spare cell in this paper. Before Engineering Change Order (ECO) is applied, these cells are pre-placed as decoupling capacitors. When ECO is applied, these cells are configured as functional cells. To demonstrate the efficiency of our configurable cell, we propose an algorithm for timing closure and IR drop minimization. Compared with traditional ECO flow, our method shows 16% reduction in maximum IR drop and 56% reduction in leakage before applying ECO, and 8% reduction in maximum IR drop after applying ECO, with 10% area of spare cells. In addition, we show that there are less unsolved ECO timing paths left after applying our ECO timing optimization algorithm due to free selection of ECO gate type.

REFERENCES

• 1: Patrik Larsson, "Parasitic Resistance in an MOS Transistor Used as On-Chip Decoupling Capacitance," IEEE Journal of Solid-State Circuits, vol. 32, no. 4, April 1997, pp. 574--576.
• 2: Neil Weste and David Harris, "A circuits and Systems Perspective(3rd Edition)," Addison Wesley
• 3: H. B. Bkoglu, "Circuits, Interconnections, and Packaging for VLSI," Addison Wesley, 1990.
• 4: http://www.cerc.utexas.edu/itc99-benchmarks/bench.html, Benchmark Suite for ITC 1999.
• 5: http://www.cadence.com/, Manual of SOC Encounter 2007.
• 6: Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang, "ECO Timing Optimization Using Spare Cells," International Conference on Computer Aided Design, 2007, pp. 530--535.
• 7: S. Pant, D. Blaauw, V. Zolotov, S. Sundareswaran, and R. Panda, "Vectorless Analysis of Supply Noise Induced Delay Variation," International Conference on Computer-Aided Design, 2003, pp. 184--190.
• 8: Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang and Malgorzata Marek-Sadowska, "Engineering Change Using Spare Cells with Constant Insertion," International Conference on Computer-Aided Design, 2007, pp. 544--547.
• 9: Haihua Su, Sachin S. Sapatnekar and Sani R. Nassif, "An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts," Proceedings of the International Symposium on Physical Design, 2002, pp. 68--73.
• 10: Chih-chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska and Kwang-Ting Cheng, "Logic Synthesis for Engineering Change," Conference on Design Automation Conference, 1995, pp. 647--652.
• 11: Sanjay Pant and David Blaauw, Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks," Conference on Design Automation Conference, 2007, pp. 757--762.
• 12: Hang Li, Zhenyu Qi, Tan, S. X. D., Lifeng Wu, Yici Cai and Xianlong Hong "Partitioning-Based Approach to Fast On-Chip Decap Budgeting and Minimization," Conference on Design Automation Conference, 2005, pp. 170--175.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout

General Terms:
Algorithms, Design

Keywords:
ECO, IR drop, decoupling capacitor, spare cell