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Statistical multilayer process space coverage for at-speed test
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents
San Francisco, California
SESSION: Speed path identification and silicon debug table of contents
Pages 340-345  
Year of Publication: 2009
ISBN:978-1-60558-497-3
Authors
Jinjun Xiong  IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Yiyu Shi  UCLA, CA
Vladimir Zolotov  IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Chandu Visweswariah  IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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ABSTRACT

Increasingly large process variations make selection of a set of critical paths for at-speed testing essential yet challenging. This paper proposes a novel multilayer process space coverage metric to quantitatively gauge the quality of path selection. To overcome the exponential complexity in computing such a metric, this paper reveals its relationship to a concept called order statistics for a set of correlated random variables, efficient computation of which is a hitherto open problem in the literature. This paper then develops an elegant recursive algorithm to compute the order statistics (or the metric) in provable linear time and space. With a novel data structure, the order statistics can also be incrementally updated. By employing a branch-and-bound path selection algorithm with above techniques, this paper shows that selecting an optimal set of paths for a multi-million-gate design can be performed efficiently. Compared to the state-of-the-art, experimental results show both the efficiency of our algorithms and better quality of our path selection.


REFERENCES

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