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Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions
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Proceedings of the 46th Annual Design Automation Conference table of contents
San Francisco, California
SESSION: Emerging technologies: blue-sky research or CMOS replacement? table of contents
Pages 304-309  
Year of Publication: 2009
ISBN:978-1-60558-497-3
Authors
Nishant Patil  Stanford University, Stanford, CA
Albert Lin  Stanford University, Stanford, CA
Jie Zhang  Stanford University, Stanford, CA
H.-S. Philip Wong  Stanford University, Stanford, CA
Subhasish Mitra  Stanford University, Stanford, CA
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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ABSTRACT

Carbon Nanotube Field-Effect Transistors (CNFETs) show promise as extensions to silicon-CMOS. Ideal CNFET circuits can potentially provide 20X Energy-Delay-Product benefits over silicon-CMOS at the 16 nm technology node. However, several challenges must be overcome before such performance benefits can be experimentally realized. In this paper, we present a brief overview of CNFET technology, and address commonly raised concerns through a series of Frequently Asked Questions (FAQs). We also provide a CNFET technology outlook which includes a survey of challenges as well as existing and potential solutions to these challenges.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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