Soft connections

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Soft connections: addressing the hardware-design modularity problem

Full text

Pdf (122 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents

San Francisco, California

SESSION: Design flexibility: bend it, shape it, anyway you want it! table of contents

Pages 276-281

Year of Publication: 2009

ISBN:978-1-60558-497-3

Authors

Michael Pellauer	Massachusetts Institute of Technology
Michael Adler	Intel Corporation
Derek Chiou	University of Texas at Austin
Joel Emer	Massachusetts Institute of Technology and Intel Corporation

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 13, Citation Count: 0

Additional Information:

abstract references index terms

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1629911.1629986 What is a DOI?

ABSTRACT

Hardware-design languages typically impose a rigid communication hierarchy that follows module instantiation. This leads to an undesirable side-effect where changes to a child's interface result in changes to the parents. Soft connections address this problem by allowing the user to specify connection endpoints that are automatically connected at compilation time, rather than by the user.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Pellauer, M. Adler, J. Emer, Modular Soft Connections. Computation Structures Group Technical Report #505, MIT.
	2	M. Pellauer, M. Vijayaraghavan, M. Adler, Arvind and J Emer. Quick Performance Models Quickly: Timing-Directed Simulation on FPGAs. In Proceedings of ISPASS, 2008.
	3	Bluespec Inc. http://www.bluespec.com/, 2008.
	4	D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. H. Reinhart, D. E. Johnson, J. Keefe, and H. Angepat. FPGA-accelerated simulation technologies FAST: Fast, full-system, cycle-accurate simulators. In MICRO, 2007.
	5	D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. H. Reinhart, D. E. Johnson, and Z. Xu. The FAST methodology for high-speed SoC/Computer simulation. In Proceedings of ICCAD, 2007.
	6	E. Chung, E. Nurvitadhi, J. Hoe K. Mai, and B. Falsafi. Accelerating Architectural-level, Full-System Multiprocessor Simulations using FPGAs. In FPGA '08: 11th International Symposium on Field Programmable Gate Arrays, 2008.
	7	Nallatech, Inc. http://www.nallatech.com/, 2009.
	8	HiTech Global, LLC. http://www.hitechglobal.com/, 2009.
	9	M. Pellauer, M. Vijayaraghavan, M. Adler, Arvind, and J. Emer. APorts: an efficient abstraction for cycle-accurate performance models on FPGAs. In FPGA '08: 11th International Symposium on Field Programmable Gate Arrays, 2008.
	10	D. Rosenband and Arvind. Modular Scheduling of Guarded Atomic Actions. In Proceedings of DAC, San Diego, CA, 2004.
	11	J. Wawrzynek, D. Patterson, M. Oskin, S. L. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, and K. Asanovic. RAMP: a research accelerator for multiple processors. IEEE Micro, Mar/Apr 2007.