Trace-driven workload simulation method for Multiprocessor System-On-Chips

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Trace-driven workload simulation method for Multiprocessor System-On-Chips

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents

San Francisco, California

SESSION: Timing simulation: optimized embedded software and MPSOCs table of contents

Pages 232-237

Year of Publication: 2009

ISBN:978-1-60558-497-3

Authors

Tsuyoshi Isshiki	Tokyo Institute of Technology, Tokyo, Japan
Dongju Li	Tokyo Institute of Technology, Tokyo, Japan
Hiroaki Kunieda	Tokyo Institute of Technology, Tokyo, Japan
Toshio Isomura	Toyota Motor Corporation, Toyota, Japan
Kazuo Satou	Toyota Motor Corporation, Toyota, Japan

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems

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ACM New York, NY, USA

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Downloads (6 Weeks): 25, Downloads (12 Months): 25, Citation Count: 0

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ABSTRACT

While Multiprocessor System-On-Chips (MPSoCs) are becoming widely adopted in embedded systems, there is a strong need for methodologies that quickly and accurately estimate performance of such complex systems. In this paper, we present a novel method for accurately estimating the cycle counts of parameterized MPSoC architectures through workload simulation driven by program execution traces encoded in the form of branch bitstreams. Experimental results show that the proposed method delivers a speedup factor of 70.15 to 238.58 against the instruction-set simulator based method while achieving high cycle accuracy whose estimation error ranges between 0.016% and 0.459%.

REFERENCES

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