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MPTLsim: a simulator for X86 multicore processors

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents

San Francisco, California

SESSION: Timing simulation: optimized embedded software and MPSOCs table of contents

Pages 226-231

Year of Publication: 2009

ISBN:978-1-60558-497-3

Authors

Hui Zeng	State University of New York, Binghamton, NY
Matt Yourst	State University of New York, Binghamton, NY
Kanad Ghose	State University of New York, Binghamton, NY
Dmitry Ponomarev	State University of New York, Binghamton, NY

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

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ABSTRACT

Current microprocessors are effectively a system-on-a-chip, as they incorporate processing cores, interconnections, shared and private caches and DRAM controllers on a single die. Consequently, it is imperative to have fast and accurate simulation tools for such systems; this paper such a tool for simulating all current and announced variants of multicore processors that use the predominant PC (X86, X86-64) instruction set, as well as external DRAM memory and buses. We discuss the major techniques used for speeding up the simulation and improving the overall accuracy, and the simulation of system-level details such as coherent caches, on-chip interconnections, memory bus and DRAM. We also demonstrate a 8-fold speedup against a widely-used popular tool.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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