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ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents
San Francisco, California
SESSION: Low-power design and analysis techniques table of contents
Pages 172-177  
Year of Publication: 2009
ISBN:978-1-60558-497-3
Authors
Cedric Walravens  K.U. Leuven - ESAT-MICAS, Heverlee, Belgium
Yves Vanderperren  K.U. Leuven - ESAT-MICAS, Heverlee, Belgium
Wim Dehaene  K.U. Leuven - ESAT-MICAS, Heverlee, Belgium
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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ABSTRACT

Today's highly integrated System-on-Chips (SoC) demand innovative architectural modeling means to cope with their energy constraints. In this context, SystemC has become a well-established simulation tool for Transaction Level Modeling (TLM) in the integrated electronics industry but it lacks the support for power modeling. This paper introduces ActivaSC, a flexible, fast, transparent and non-intrusive extension to the SystemC class library which allows capturing the activity information of a digital system being modeled. This information can then be post-processed to estimate power consumption. ActivaSC avoids time consuming design iterations as designers can assess architectural design trade-offs based on system activity early in the design flow. ActivaSC does not require any code alterations nor a specific API, so that it can be used with any modeling style. Finally, several benchmark tests illustrate the superior efficiency of ActivaSC. A speed-up of up to 75% in terms of elaboration overhead and 20% in terms of simulation overhead is realized with respect to prior art.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A. Abril et al. Energy estimation and optimization in architectural descriptions of complex embedded systems. In VLSI Circ. and Syst. II, volume 5837 of Proc. SPIE, pages 456--466, Seville, Spain, May 2005.
 
2
B. Arts, L. Benini, N. van der Eng, M. Heijligers, A. Kenter, E. Macii, H. Munk, and F. Theeuwen. Enhancing behavioural-level design flows with statistical power estimation capabilities. Comp. and Dig. Tech., IEE Proc., 152(6):731--737, Nov. 2005.
 
3
J. Aynsley. Here's Exactly What You Can Do with the New SystemC Standard! Doulos Ltd., 2006.
 
4
J. Aynsley. Dealing with Deprecated Features in SystemC 2.2. Doulos Ltd., 2007.
 
5
L. Benini and G. de Micheli. System-level power optimization: techniques and tools. ACM Trans. Des. Autom. Electron. Syst., 5(2):115--192, 2000.
 
6
D. C. Black and J. Donovan. SystemC from the Ground Up. Springer, 2nd edition, 2004.
 
7
K. Buyuksahin and F. Najm. Early power estimation for VLSI circuits. CAD of Integrated Circ. and Syst., IEEE Trans. on, 24(7):1076--1088, July 2005.
 
8
L. Cai and D. Gajski. Transaction level modeling: an overview. In CODES+ISSS '03, pages 19--24. ACM, Oct 1--3 2003.
 
9
R. Damasevicius. Estimation of design characteristics at rtl modeling level using SystemC. Information Tech. and Control, 35(2):117--123, 2006.
 
10
L. Goldthwaite. Technical report on C++ performance. Technical Report N1666, ISO/IEC, July 2004.
 
11
IEEE Computer Society. IEEE Standard SystemC Language Reference Manual, IEEE Std 1666#8482;-2005 edition, 31 March 2006.
 
12
M. Keating et al. Low Power Methodology Manual for System-on-Chip Design. Springer, 2007.
 
13
F. Klein, G. Araujo, R. Azevedo, R. Leao, and L. dos Santos. An efficient framework for high-level power exploration. Circ. and Syst., 2007. MWSCAS 2007. 50th Midwest Symposium on, pages 1046--1049, Aug. 2007.
 
14
F. Klein, G. Araujo, R. Azevedo, R. Leao, and L. C. V. dos Santos. A multi-model power estimation engine for accuracy optimization. In ISLPED '07: Proc. 2007 Int. Symp. on Low Power Electronics and Design, pages 280--285, New York, NY, USA, 2007. ACM.
 
15
W. Klingauf and M. Geffken. Design structure analysis and transaction recording in systemc designs: A minimal-intrusive approach. In FDL, Sep. 2006.
 
16
P. Landman and J. Rabaey. Activity-sensitive architectural power analysis. CAD of Integrated Circ. and Syst., IEEE Trans. on, 15(6):571--587, Jun 1996.
 
17
H. Lebreton and P. Vivet. Power modeling in SystemC at transaction level, application to a DVFS architecture. Symp. on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual, pages 463--466, April 2008.
 
18
T. G. Noll. Application specific eFPGAs for SoC platforms. In International Symposium on IEEE VLSI Design, Automation and Test, VLSI-TSA, page 28, 2005.
 
19
Open SystemC Initiative. http://www.systemc.org.
 
20
SOCcentral. SystemC and ESL continue gaining momentum in 2007. http://www.soccentral.com/results.asp?EntryID=22441.
 
21
B. Stroustrup. The C++ Programming Guide. Addison Wesley, 1997.
 
22
G. Zhang et al. The paradigm of "more than Moore". Electronic Packaging Technology, 2005 6th Int. Conf. on, pages 17--24, 2005.
 
23
L. Zhong. RTL-aware cycle-accurate functional power estimation. CAD of Integrated Circ. and Syst., IEEE Trans. on, 25(10):2103--2115, 2006.