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ABSTRACT

In this paper we propose a new methodology, called parametric on chip variation (POCV) analysis, to determine local process variation effects on the timing of designs. The proposed methodology requires relative delay and parasitic variations of cells and interconnects, respectively. Once this information is provided, delays and arrival times are propagated to calculate slacks as a function of these relative variations. A key characteristic of the POCV analysis is that it does not require a statistical library characterization or statistical RC extraction. The POCV method has been implemented in a timing analysis software, and tested on multiple production designs on 65nm and 45nm technology nodes, including multi-million instance designs. Our observation was that compared to the existing methods, POCV removes unrealistical pessimism on the setup paths and captures risks on the hold paths, with no changes to the existing timing sign-off environment.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

General Terms:
Algorithms, Design, Performance

Keywords:
on chip variation (OCV), parametric analysis, timing