A parametric approach for handling local variation effects in timing analysis

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A parametric approach for handling local variation effects in timing analysis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents

San Francisco, California

SESSION: Statistical methods in static timing analysis table of contents

Pages 126-129

Year of Publication: 2009

ISBN:978-1-60558-497-3

Authors

Ayhan Mutlu	Extreme DA Corporation, Santa Clara, CA
Jiayong Le	Extreme DA Corporation, Santa Clara, CA
Ruben Molina	Extreme DA Corporation, Santa Clara, CA
Mustafa Celik	Extreme DA Corporation, Santa Clara, CA

Sponsors

EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 17, Downloads (12 Months): 17, Citation Count: 0

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ABSTRACT

In this paper we propose a new methodology, called parametric on chip variation (POCV) analysis, to determine local process variation effects on the timing of designs. The proposed methodology requires relative delay and parasitic variations of cells and interconnects, respectively. Once this information is provided, delays and arrival times are propagated to calculate slacks as a function of these relative variations. A key characteristic of the POCV analysis is that it does not require a statistical library characterization or statistical RC extraction. The POCV method has been implemented in a timing analysis software, and tested on multiple production designs on 65nm and 45nm technology nodes, including multi-million instance designs. Our observation was that compared to the existing methods, POCV removes unrealistical pessimism on the setup paths and captures risks on the hold paths, with no changes to the existing timing sign-off environment.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. R. Nassif, "Design for variability in DSM technologies," ISQED Proceedings, pp. 451--454, 2000.
	2	A. Mutlu, K. Le, M. Celik, D. Tsien, G. Shyu, L. C. Yeh, "An exploratory study on statistical timing analysis and parametric yield optimization," ISQED Proceedings, pp. 677--684, 2007.
	3	C. Bittlestone, A. Hill, V. Singhal, Arvind N. V., "Architecting ASIC Libraries and Flows in Nanometer Era," DAC Proceedings, pp. 776--781, 2003.
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	5	H. Chang, S. Sapatnekar, "Statistical timing analysis under spatial correlations," IEEE Trans. on CAD of Integrated Circuits and Systems, pp. 1467--1482, 2005.
	6	J. Le, "Parametric Cell Delay Models and their Applications in 65/45nm Digital Designs," Electrical Cell Modeling Workshop in IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, November, 2008.