ACM Home Page
Please provide us with feedback. Feedback
Carbon nanotube circuits in the presence of carbon nanotube density variations
Full text PdfPdf (289 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents
San Francisco, California
SESSION: Design and optimization of nanocircuits table of contents
Pages 71-76  
Year of Publication: 2009
ISBN:978-1-60558-497-3
Authors
Jie Zhang  Stanford University, Stanford, CA
Nishant Patil  Stanford University, Stanford, CA
Arash Hazeghi  Stanford University, Stanford, CA
Subhasish Mitra  Stanford University, Stanford, CA
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 13,   Downloads (12 Months): 13,   Citation Count: 0
Additional Information:

abstract   references   index terms  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1629911.1629933
What is a DOI?

ABSTRACT

Carbon Nanotubes (CNTs) are grown using chemical synthesis. As a result, it is extremely difficult to ensure exact positioning and uniform density of CNTs. Density variations in CNT growth can compromise reliability of Carbon Nanotube Field Effect Transistor (CNFET) circuits, and result in increased delay variations. A parameterized model for CNT density variations is presented based on experimental data extracted from aligned CNT growth. This model is used to quantify the impact of such variations on design metrics such as noise margin and delay variations of CNFET circuits. Finally, we analyze correlation that exists in aligned CNT growth, and demonstrate how the reliability of CNFET circuits can be significantly improved by taking advantage of such correlation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
[Amlani 06] Amlani, I., et al., "First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier," Proc. IEDM, pp. 1--4, 2006
 
2
[Bobba 09] Bobba, S. et al., "Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis", Proc. DATE, 2009.
 
3
[Borkar 05] Borkar, S., et al., "Statistical circuit design with carbon nanotubes", U.S. Patent Application 20070155065, 2005.
 
4
[Cameron 98] Cameron, A. C. and P. K. Trivedi, Regression Analysis of Count Data, Cambridge University Press, 1998.
 
5
[Collins 01] Collins, P., S. Arnold, P. Avouris, "Engineering carbon nanotubes and nanotube circuits using electrical breakdown", Science, vol. 292, pp. 706--709, 2001.
 
6
[Chang 03] Chang, H. and S. Sapatnekar, "Statistical timing analysis considering spatial correlation in a PERT-like traversal," Proc. ICCAD, pp. 621--625, 2003.
 
7
[Cox 62] Cox, D. R., Renewal Theory, Methuen & Co, 1962.
 
8
[Dai 02] Dai, H., "Carbon Nanotubes: Synthesis, Integration, and Properties," Acc. Chem. Res., 35, 1035--1044, 2002.
 
9
[Deng 07a] Deng, J., et al., "Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections", Proc. ISSCC, pp. 70--588, 2007.
 
10
[Deng 07b] Deng, J., and H. -S. P. Wong, "A Compact SPICE Model for Carbon Nanotube Field Effect Transistors Including Non-Idealities and Its Application --- Part I: Model of the Intrinsic Channel Region", IEEE Trans. Elec. Dev., pp. 3186--3194, 2007.
 
11
[Kang 07] Kang, S. J., et al., "High-Performance Electronics Using Dense, Perfectly Aligned Arrays of Single-Walled Carbon Nanotubes", Nature Nanotechnology, vol. 2, pp. 230--236, 2007.
 
12
[Kocabas 07] Kocabas, C., et al., "Improved Synthesis of Aligned Arrays of Single-Walled Carbon Nanotubes and Their Implementation in Thin Film Type Transistors", Journal of Physical Chemistry C 111(48), 17879--17886 (2007).
 
13
[Kshirsagar 08] Kshirsagar, C., H. Li, T. Kopley, and K. Banerjee, "Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect", IEEE Electron Device Letters, Vol. 29, No. 12, pp. 1408--1411, 2008.
 
14
[Lohstroh 83] Lohstroh, J., E. Seevinck, and J. D. Groot, "Worst-Case Static Noise Margin Criteria for Logic Circuits and Their Mathematical Equivalence", JSSC, No. 6, pp. 803--806, 1983.
 
15
[Mitra 09] Mitra, S., et al., "Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube Field Effect Transistors", Proc. DATE, 2009.
 
16
[Nieuwoudt 07] Nieuwoudt, A., and Y. Massoud, "On the Impact of Process Variations for Carbon Nanotube Bundles for VLSI Interconnect," IEEE Trans. Elec. Dev., Vol. 54, No. 3, 2007
 
17
[Patil 08a] Patil, N., et al., "Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures," Symp. VLSI Tech., pp. 205--206, 2008.
 
18
[Patil 08b] Patil, N., et al., "Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits," IEEE Trans. Computer-Aided Design, pp. 1725--1736, 2008.
 
19
[Patil 09] Patil, N., et al., "Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions", Proc. DAC, 2009.
 
20
[Ross 01] Ross, S. M., A First Course in Probability, Prentice Hall, 2001.
 
21
[Ross 05] Ross, S. M., Introductory Statistics, Academic Press, 2005.
 
22
[Zhang 06] Zhang, G., et al., "Selective Etching of Metallic Carbon Nanotubes by Gas-Phase Reaction", Science, Vol. 314, pp. 974--977, 2006.
 
23
[Zhang 08] Zhang, J., N. Patil, and S. Mitra, "Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits", Proc. DATE, pp. 1009--1014, 2008.