ACM Portal
  Subscribe (Full Service)    Register (Limited Service, Free)    Login
  Search:   The ACM Digital Library   The Guide
  
ACM Home Page
Please provide us with feedback. Feedback
Use of lithography simulation for the calibration of equation-based design rule checks
Full text PdfPdf (239 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 46th Annual Design Automation Conference table of contents
San Francisco, California
SESSION: Novel design and verification methodologies table of contents
Pages 67-70  
Year of Publication: 2009
ISBN:978-1-60558-497-3
Authors
David Abercrombie  Mentor Graphics Corp., Wilsonville, OR
Fedor Pikus  Mentor Graphics Corp., Wilsonville, OR
Cosmin Cazan  Mentor Graphics Corp., Wilsonville, OR
Sponsors
EDAC : Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 7,   Citation Count: 0
Additional Information:

abstract   references   index terms  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1629911.1629931
What is a DOI?

ABSTRACT

Designers using one-dimension measurements in nanometer designs can't readily identify features prone to excessive variation during processing. Process simulation provides high resolution checking, but requires significant computing resources. Equation-based design rule checking (eqDRC) offers the DRC performance with capture of complex process issues using multi-dimensional equations. One challenge to adopting eqDRC is the definition and calibration of the equations. We will show how a lithographic simulator can be used to define and calibrate an eqDRC equation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. S. Fathy, M. Al-Imam, et al. "Litho Aware Method for Circuit Timing/Power Analysis through Process". Proc. SPIE 6521, 65210O (2007)
 
2
Burden, R. L., Faires D. and Reynolds A. C. (1981): Numerical Analysis, (2nd ed.), PWS Publishers. Boston, Massachusetts.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids


General Terms:
Design, Measurement, Verification


Keywords:
DFM, DRC, LFD, Leff, equation based DRC, lithography, manufacturability, verification


The ACM Portal is published by the Association for Computing Machinery. Copyright © 2009 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player