Circuit techniques for dynamic variation tolerance

ABSTRACT

Three circuit techniques for dynamic variation tolerance are presented: (i) Sensors with adaptive voltage and frequency circuits, (ii) Tunable replica circuits for timing-error prediction with error recovery, and (iii) Embedded error-detection sequential circuits with error recovery. These circuits mitigate the clock frequency guardbands for dynamic variations, thus improving microprocessor performance and energy-efficiency. These circuits are described with a focus on the different trade-offs in guardband reduction and design overhead. Opportunities for CAD to further enhance microprocessor performance and energy efficiency are offered.

REFERENCES

• 1: A. Muhtaroglu, et al., "On-Die Droop Detector for Analog Sensing of Power Supply Noise," IEEE J. Solid-State Circuits, pp. 651--660, Apr. 2004.
• 2: J. Tschanz, et al., "Tunable Replica Circuits and Adaptive Voltage-Frequency Techniques for Dynamic Voltage, Temperature, and Aging Variation Tolerance," in IEEE Symp. VLSI Circuits, June 2009.
• 3: T. Fischer, et al., "A 90-nm Variable Frequency Clock System for a Power-Managed Itanium Architecture Processor," IEEE J. Solid-State Circuits, pp. 218--228, Jan. 2006.
• 4: R. McGowen, et al., "Power and Temperature Control on a 90-nm Itanium Family Processor," IEEE J. Solid-State Circuits, pp. 229--237, Jan. 2006.
• 5: J. Tschanz, et al., "Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 292--293.
• 6: J. Keane, et al., "An On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation," in Proc. ISLPED, Aug. 2007, pp. 189--194.
• 7: E. Karl, et al., "Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 410--411.
• 8: T. Kim, et al., "Silicon Odometer: An On-chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits," IEEE J. Solid-State Circuits, pp. 874--880, Apr. 2008.
• 9: A. Cabe, et al., "Small Embeddable NBTI Sensors (SENS) for Tracking On-Chip Performance Decay," in IEEE ISQED, Mar. 2009, pp. 1--6.
• 10: A. Drake, et al., "A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 398--399.
• 11: P. Franco and E. J. McCluskey, "Delay Testing of Digital Circuits by Output Waveform Analysis," in Proc. IEEE Intl. Test Conf., Oct. 1991, pp. 798--807.
• 12: P. Franco and E. J. McCluskey, "On-Line Testing of Digital Circuits," in Proc. IEEE VLSI Test Symp, Apr. 1994, pp. 167--173.
• 13: M. Nicolaidis, "Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies," in Proc. IEEE VLSI Test Symp., Apr. 1999, pp. 86--94.
• 14: D. Ernst, et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," in Proc. IEEE/ACM Intl. Symp. Microarchitecture (MICRO-36), Dec. 2003, pp. 7--18.
• 15: S. Das, et al., "A Self-Tuning DVS Processor Using Delay-Error Detection and Correction," IEEE J. Solid-State Circuits, pp. 792--804, Apr. 2006.
• 16: S. Das, et al., "Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance," IEEE J. Solid-State Circuits, pp. 32--48, Jan. 2009.
• 17: K. A. Bowman, et al., "Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance," IEEE J. Solid-State Circuits, pp. 49--63, Jan. 2009.
• 18: V. Srinivasan, et al., "Optimizing Pipelines for Power and Performance," in Proc. Intl. Symp. Microarchitecture (MICRO-35), Nov. 2002, pp. 333--344.
• 19: A. Hartstein and T. R. Puzak, "The Optimum Pipeline Depth Considering Both Power and Performance," ACM Trans. Arch. and Code Opt. (TACO), pp. 369--388, Dec. 2004.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Performance, Reliability

Keywords:
dynamic variations, error correction, error detection, error recovery, error-detection sequential, parameter variations, replica paths, resilient circuits, timing errors, variation sensors, variation-tolerant circuits