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Bottom-up performance analysis considering time slice based software scheduling at system level
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International Conference on Hardware Software Codesign archive
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis table of contents
Grenoble, France
SESSION: Perfomance analysis and optimization for heterogeneous multiprocesses system table of contents
Pages 423-432  
Year of Publication: 2009
ISBN:978-1-60558-628-1
Authors
Alexander Viehl  FZI Forschungszentrum Informatik, Karlsruhe, Germany
Michael Pressler  FZI Forschungszentrum Informatik, Karlsruhe, Germany
Oliver Bringmann  FZI Forschungszentrum Informatik, Karlsruhe, Germany
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, a novel approach for integrating time slice based resource access in global performance analysis of distributed real-time critical embedded systems is presented. The performance analysis approach itself is based on bottom-up analysis of communicating processes under consideration of synchronization by inter-process communication and complex internal control flows of the processes. This general analysis methodology is extended concerning concurrent occupation of shared resources using time slice based access methods. The defined extensions are parameterizable for describing arbitrary communication media access schedules and software schedules on shared computation resources, although the explicit focus in this paper is on software scheduling. The applicability of the analysis extensions is presented by a case study of a multimedia subsystem implemented in SystemC.


REFERENCES

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1
G. Agosta, F. Bruschi, and D. Sciuto. Static Analysis of Transaction-Level Communication Models. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27, 2008.
 
2
K. Albers, F. Bodmann, and F. Slomka. Hierarchical event streams and event dependency graphs: A new computational model for embedded real-time systems. In ECRTS '06: Proceedings of the 18th Euromicro Conference on Real-Time Systems, 2006.
 
3
F. L. Baccelli, G. Cohen, G. J. Olsder, and J.-P. Quadrat. Synchronization and linearity, 1992.
 
4
A. Donlin. Transaction level modeling: Flows and use models. In CODES+ISSS'04: Proceedings of the 2nd International Conference on Hardware/Software Codesign and System Synthesis, 2004.
 
5
J. Falk, J. Keinert, C. Haubelt, J. Teich, and S. S. Bhattacharyya. A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. In EMSOFT '08: Proceedings of the 7th ACM international conference on Embedded software, 2008.
 
6
M. Gonzalez Harbour, J. Gutierrez Garcia, J. Palencia Gutierrez, and J. Drake Moyano. Mast: Modeling and analysis suite for real time applications. In Proc. Real-Time Systems, 13th Euromicro Conference on, 2001.
 
7
M. Hendriks and M. Verhoef. Timed automata based analysis of embedded system architectures. 20th International Parallel and Distributed Processing Symposium IPDPS, 2006.
 
8
A. Hergenhan and W. Rosenstiel. Static Timing Analysis of Embedded Software on Modern Processor Architectures. In Proceedings of the Design, Automation and Test in Europe Conference (DATE), 2000.
 
9
KaSCPar Karlsruhe SystemC Parser Home. www.fzi.de/sim/kascpar.html.
 
10
M. Krause, O. Bringmann, and W. Rosenstiel. Target Software Generation: An Approach for Automatic Mapping of SystemC Specifications onto Real-Time Operating Systems. Springer: Design Automation for Embedded Systems, 2007.
 
11
C. Liu and J. W. Layland. Scheduling algorithms for multiprogramming in hard-real-time environment. Journal of the Association for Computing Machinery, 1973.
 
12
T. Pop, P. Pop, P. Eles, and Z. Peng. Bus access optimisation for flexray-based distributed embedded systems. In DATE '07: Proceedings of the conference on Design, automation and test in Europe, 2007.
 
13
R. Racu, L. Li, R. Henia, A. Hamann, and R. Ernst. Improved response time analysis of tasks scheduled under preemptive Round-Robin. In CODES+ISSS'07: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007.
 
14
G. Schirner, A. Gerstlauer, and R. Domer. Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. In ASP-DAC '07: Proceedings of the 2007 conference on Asia South Pacific design automation, 2007.
 
15
J. Schnerr, O. Bringmann, A. Viehl, and W. Rosenstiel. High-Performance Timing Simulation of Embedded Software. In Proceedings of the Design Automation Conference (DAC), 2008.
 
16
A. Siebenborn, A. Viehl, O. Bringmann, and W. Rosenstiel. Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. In ASPDAC'07: Proceedings of the 12th Asia and South Pacific Design Automation Conference, 2007.
 
17
A. Viehl, M. Pressler, O. Bringmann, and W. Rosenstiel. White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling. In Proceedings of the Design, Automation, and Test in Europe Conference (DATE), 2009.
 
18
A. Viehl, B. Sander, O. Bringmann, and W. Rosenstiel. Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties. In Proceedings of the Forum on Specification, Verification, and Design Languages (FDL), 2008.
 
19
E. Wandeler and L. Thiele. Optimal TDMA time slot and cycle length allocation for hard real-time systems. In ASP-DAC '06: Proceedings of the 2006 conference on Asia South Pacific design automation, 2006.
 
20
A. Yakovlev, L. Gomes, and L. Lavagno. Hardware Design and Petri Nets. Kluwer, 2000.