Stack oriented data cache filtering

ABSTRACT

The L1 data cache is one of the most frequently accessed structures in the processor. Because of this and its moderate size it is a major consumer of power. In order to reduce its power consumption, in this paper a small filter structure that exploits the special features of the references to the stack region is proposed. This filter, which acts as a top -non-inclusive- level of the data memory hierarchy, consists of a register set that keeps the data stored in the neighborhood of the top of the stack. Our simulation results show that using a small Stack Filter (SF) of only a few registers, 15% to 30% data cache power savings can be achieved on average, with a negligible performance penalty.

REFERENCES

• 1: Viredaz, M.A., Wallach, D.A.: Power evaluation of a handheld computer. IEEE Micro 23(1) (January 2003) 66--74
• 2: Montanaro, J., et al.: A 160 Mhz, 32-b, 0.5W CMOS RISC Microprocessor. Digital Technology Journal 9(1) (1997) 49--62
• 3: Ghose, K., Kamble, M.B.: Reducing Power in Superescalar Processors Caches using Su-banking, Multiple Line Buffers and Bit-Line Segmentation. In: International Symposium on Low-Power Electronics and Design. (August 1999) 70--75
• 4: Su, C.L., Despain, A.M.: Cache Designs for Energy-Efficiency. In: Hawaii International Conference on Systems Sciences. (January 1995) 306--314
• 5: Racunas, P., Patt, Y.N.: Partitioned First-Level Cache Design for Clustered Microarchitectures. In: International Conference on Supercomputing, San Francisco, California (June 2003) 22---31
• 6: Kin, J., Gupta, M., Mangione-Smith, W.: The Filter Cache: An Energy Efficient Memory Structure. In: International Symposium on Microarchitecture, Research Triangle Park, North Carolina (December1997) 184--193
• 7: Albonesi, D.: Selective Cache Ways: On-Demand Cache Resource Allocation. Journal of Instruction-Level Parallelism 2 (2000)
• 8: Lee, L.H., Moyer, B., Arends, J.: Instruction Fetch Energy Reduction Using Loop Caches for Embedded Applications with Small Tight Loops. In: International Symposium on Low-Power Electronics and Design, San Diego, California (August 1999) 267--269
• 9: Lee, H., Smelyanskiy, M., Newburn, C., Tyson, G.: Stack Value File: Custom Microarchitecture for the Stack. In: International Symposium on High-Performance Computer Architecture, Monterey, Mexico (January 2001) 5--14
• 10: Cho, S., Yew, P., Lee, G.: Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor. In: International Symposium on Computer Architecture, Atlanta, Georgia (May 1999) 100--110
• 11: Ward, Halstead: Computation Structures. Kluwer Academics (2002)
• 12: Ballapuram, C.S., Sharif, A., Lee, H.S.: Exploiting Access Semantics and Program Behavior to Reduce Snoop Power in Chip Multiprocessors. In:
• 13: Architectural Support for Programming Languages and Operating Systems, Seattle, Washington (March 2008) 60--69
• 14: Mudge, T., Austin, T., Grunwald, D., et al.: A SimpleScalar-Arm Power Modeling Project http://www.eecs.umich.edu/Üpanalyzer.
• 15: Austin, T., Larson, E., Ernst, D.: SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer 39(2) (February 2002) 59--67
• 16: Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: Mibench:a Free, Commercially Representative Embedded Benchmark Suite. In: Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop, Washington (December 2001) 3--14
• 17: Kim, N.S., Austin, T., Mudge, T., Grunwald, D.: Challenges for Architectural Level Power Modeling. Kluwer Academics (2002)
• 18: Thoziyoor, S., Muralimanohar, N., Ahn, J., Jouppi, N.: CACTI 5.1. Technical report, HP Laboratories, Palo Alto (April 2008)
• 19: Ditzel, D.R., McLellan, H.R.: Register Allocation for Free: The C Machine Stack Cache. SIGARCH Computer Architecture News 10(2) (1982) 48--56
• 20: Huang, M., Renau, J., Torrellas, J.: L1 Data Cache Decomposition for Energy Efficiency. In: International Symposium on Low-Power Electronics and Design, Huntington Beach, California (August 2001) 10--15
• 21: Geiger, M., McKee, S., Tyson, G.: Beyond Basic Region Caching: Specilalizing Cache Structures for High Performance and Energy Consevation. Hipeac 2005 (2005)
• 22: Hemsath, A., Morton, R., Sjodin, J.: Implementing a Stack Cache. Technical report, Rice University (June 2007)

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

General Terms:
Algorithms, Design, Performance

Keywords:
cache memory, memory hierarchy, power-performance efficient design