ESL power analysis of embedded processors for temperature and reliability estimations

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ESL power analysis of embedded processors for temperature and reliability estimations

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International Conference on Hardware Software Codesign archive
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis table of contents

Grenoble, France

SESSION: Synthesis and analysis for variation and reliability table of contents

Pages 239-248

Year of Publication: 2009

ISBN:978-1-60558-628-1

Authors

Björn Sander	FZI Forschungszentrum Informatik, Karlsruhe, Germany
Jürgen Schnerr	FZI Forschungszentrum Informatik, Karlsruhe, Germany
Oliver Bringmann	FZI Forschungszentrum Informatik, Karlsruhe, Germany

Sponsors

ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 26, Downloads (12 Months): 26, Citation Count: 0

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ABSTRACT

The ongoing scaling of CMOS technology facilitates the design of systems with continuously increasing functionality but also raises the susceptibility of these systems to reliability issues caused by high power densities and temperatures, respectively. Because of complexity reasons, the Electronic System Level (ESL) is gaining importance as starting point of design. Design alternatives are evaluated at ESL with respect to several design objectives, lately also including temperature. But temperatures are dominated by local power effects - a fact, that has not been sufficiently reflected at ESL until now. There is a lack of appropriate models, which we call ESL Power Density Gap. The contributions of this paper are twofold. First, we describe why the ESL Power Density Gap should be closed. In doing so, we want to stimulate a discussion. After that, we introduce a new ESL methodology for the power analysis of embedded processors, which can be considered as a first step to solve the aforementioned problem. It allows the generation of executable system models from a platform description, combining a functionality representation and component characterizations. Using an example application, it is shown that high power densities, usually invisible at ESL, can be uncovered by applying the proposed approach.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Graphviz -- Graph Visualization Software. http://www.graphviz.org.
	2	Y. Abdeddaïm, A. Kerbaa, and O. Maler. Task Graph Scheduling Using Timed Automata. In IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed Processing, 2003.
	3	Accellera Organization. Unified Power Format (UPF) Standard. http://www.unifiedpowerformat.com.
	4	Apache Design Solutions. RedHawk-SEM. http://www.apache-da.com/apache-da/Home/ProductsandSolutions/SoCPowerNoiseReliability/RedHawk-SEM.html.
	5	ARM Ltd. ARM7TDMI. http://www.arm.com/products/CPUs/ARM7TDMI.html.
	6	A. Bansal, M. Meterelliyoz, S. Singh, J. H. Choi, J. Murthy, and K. Roy. Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. In ASP-DAC '06: Proceedings of the 2006 conference on Asia South Pacific design automation, pages 237--242, 2006.
	7	R. A. Bergamaschi and Y. W. Jiang. State-Based Power Analysis for Systems-on-Chip. In Proceedings of the 40th conference on Design automation (DAC '03), pages 638--641, 2003.
	8	S. Borkar. Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. IEEE Micro, 25(6):10--16, 2005.
	9	D. Brooks, R. P. Dick, R. Joseph, and L. Shang. Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors. IEEE Micro, 27(3):49--62, 2007.
	10	Cadence Design Systems, Inc. Virtuoso UltraSIM. http://www.cadence.com/products/cic/UltraSim_fullchip.
	11	T. Chantem, R. P. Dick, and X. S. Hu. Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs. In DATE '08: Proceedings of the conference on Design, automation and test in Europe, pages 288--293, New York, NY, USA, 2008. ACM.
	12	Y. Cho, Y. Kim, S. Park, and N. Chang. System-level power estimation using an on-chip bus performance monitoring unit. In ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, pages 149--154, Piscataway, NJ, USA, 2008. IEEE Press.
	13	A. K. Coskun, T. S. Rosing, Y. Leblebici, and G. D. Micheli. A Simulation Methodology for Reliability Analysis in Multi-Core SoCs. In GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI, 2006.
	14	A. K. Coskun, T. S. Rosing, K. A. Whisnant, and K. C. Gross. Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs. IEEE Trans. Very Large Scale Integr. Syst., 16(9):1127--1140, 2008.
	15	Coware, Inc. CoWare Processor Designer. http://www.coware.com/products/processordesigner.php.
	16	I. B. Dhaou and H. Tenhunen. Efficient library characterization for high-level power estimation. IEEE Trans. Very Large Scale Integr. Syst., 12(6):657--661, 2004.
	17	DWARF Debugging Information Format Workgroup. DWARF Debugging Information Format. http://dwarfstd.org/.
	18	D. G. Fritz and R. G. Sargent. An overview of hierarchical control flow graph models. In WSC '95: Proceedings of the 27th conference on Winter simulation, pages 1347--1355, Washington, DC, USA, 1995. IEEE Computer Society.
	19	Gary Smith EDA. EDA Wallcharts 2008. http://www.garysmitheda.com.
	20	R. Goering. Automating Low Power Design -- A Progress Report. SCDsource, Special Technology Report, 2008. http://www.scdsource.com/download.php?f=SCDsource_STR_LowPower.pdf.
	21	R. Goering. Infineon's Jürgen Karmann on power and reliability. SCDsource, 2008. http://www.scdsource.com/article.php?id=239.
	22	J. Kawa, C. Chiang, and R. Camposano. EDA Challenges in Nano-scale Technology. In Custom Integrated Circuits Conference. CICC '06. IEEE, pages 236--248, 2006.
	23	A. Kumar, L. Shang, L.-S. Peh, and N. K. Jha. System-Level Dynamic Thermal Management for High-Performance Microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(1):96--108, 2008.
	24	M. Loghi, F. Angiolini, D. Bertozzi, L. Benini, and R. Zafalon. Analyzing On-Chip Communication in a MPSoC Environment. In DATE '04: Proceedings of the conference on Design, automation and test in Europe, 2004.
	25	Mentor Graphics. ModelSim. http://www.mentor.com/products/fv/modelsim/.
	26	M. J. Moran, H. N. Shapiro, B. R. Munson, and D. P. DeWitt. Introduction to Thermal Systems Engineering: Thermodynamics, Fluid Mechanics, and Heat Transfer. Wiley, 2002.
	27	N. Van Hieu. Multilevel interconnect reliability on the effects of electrothermomechanical stresses. PhD thesis, Univ. of Twente, Netherlands, 2004.
	28	V. Narayanan and Y. Xie. Reliability Concerns in Embedded System Designs. IEEE Computer, 39(1), 2006.
	29	G. Paci, P. Marchal, F. Poletti, and L. Benini. Exploring temperature-aware design in low-power MPSoCs. In DATE, 2006.
	30	Y.-H. Park, S. Pasricha, F. J. Kurdahi, and N. Dutt. Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow. In CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, pages 255--260, 2008.
	31	Y. Sakurai, H. Suzuki, K. Maemura, and S. Takakura. Present Status of the Embedded CPU in SoC Design. NEC Technical Journal, 1(5), 2006.
	32	J. Schnerr, O. Bringmann, A. Viehl, and W. Rosenstiel. High-Performance Timing Simulation of Embedded Software. In Proceedings of the 45th Design Automation Conference (DAC), pages 290--295, June 2008.
	33	A. Shakouri. Nanoscale Thermal Transport and Microrefrigerators on a Chip. Proceedings of the IEEE, 94, 2006.
	34	A. Siebenborn, A. Viehl, O. Bringmann, and W. Rosenstiel. Control-Flow Aware Communication and Conflict Analysis of Parallel Processes. In ASP-DAC '07: Proceedings of the 2007 Asia and South Pacific Design Automation Conference, 2007.
	35	Silicon Integration Initiative (Si2). Common Power Format. http://www.si2.org.
	36	K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan. Temperature-Aware Microarchitecture: Modeling and Implementation. ACM Trans. Archit. Code Optim., 1:94--125, 2004.
	37	J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. Lifetime Reliability: Toward an Architectural Solution. IEEE Micro, 25(3), 2005.
	38	Synopsys, Inc. Design Compiler and Power Compiler. http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Pages/default.aspx.
	39	Synopsys, Inc. DesignWare Building Block IP. https://www.synopsys.com/dw/doc.php/doc/dwf/manuals/dwug.pdf.
	40	Synopsys, Inc. HSIM MOS Reliability Analysis. http://www.synopsys.com/Tools/Verification/AMSVerification/DesignAnalysis/Pages/HSIMplusMOSFET.aspx.
	41	V. Tiwari, S. Malik, and A. Wolfe. Power Analysis of Embedded Software: A First Step Towards Software Power Minimization. IEEE Trans. Very Large Scale Integr. Syst., 2(4):437--445, 1994.
	42	P. van Stralen and A. D. Pimentel. Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration. In ESTImedia, pages 33--38, 2007.
	43	VaST Systems Technology. CoMET®. http://www.vastsystems.com/docs/CoMET_mar2007.pdf.
	44	J. Xi, Z. Huang, and P. Zhong. Energy Macro-Modeling of Embedded Microprocessor Using SystemC. In IEEE Int. Conf. on Electro Information Technology, 2005.