Efficient dynamic voltage/frequency scaling through algorithmic loop transformation

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Efficient dynamic voltage/frequency scaling through algorithmic loop transformation

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International Conference on Hardware Software Codesign archive
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis table of contents

Grenoble, France

SESSION: Power-aware design methodology table of contents

Pages 203-210

Year of Publication: 2009

ISBN:978-1-60558-628-1

Authors

Mohammad Ali Ghodrat	University of California, Irvine, Irvine, CA, USA
Tony Givargis	University of California, Irvine, Irvine, CA, USA

Sponsors

ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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ABSTRACT

We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for significant reduction in energy consumption. Our technique transforms loops containing nested conditional blocks. Specifically, the transformation takes advantage of the fact that the Boolean value of a conditional expression, determining the true/false paths, can be statically analyzed and this information, combined with loop dependency information, can be used to break up the original loop, containing conditional expressions, into a number of smaller loops without conditional expressions. Subsequently, each of the smaller loops can be executed at the lowest voltage/frequency setting yielding overall energy reduction. Our experiments with loop kernels from mpeg4, mpeg-decoder, mpeg-encoder, mp3, qsdpcm and gimp show an impressive energy reduction of 26.56% (average) and 66% (best case) when running on a StrongARM embedded processor. The energy reduction was obtained at no additional performance penalty.

REFERENCES

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