ACM Home Page
Please provide us with feedback. Feedback
FRA: a flash-aware redundancy array of flash storage devices
Full text PdfPdf (2.48 MB)
Source
International Conference on Hardware Software Codesign archive
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis table of contents
Grenoble, France
SESSION: Embedded software systems table of contents
Pages 163-172  
Year of Publication: 2009
ISBN:978-1-60558-628-1
Authors
Yangsup Lee  Samsung Electronics, Suwon, South Korea
Sanghyuk Jung  Hanyang University, Seoul, South Korea
Yong Ho Song  Hanyang University, Seoul, South Korea
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 43,   Downloads (12 Months): 47,   Citation Count: 0
Additional Information:

abstract   references   index terms  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1629435.1629459
What is a DOI?

ABSTRACT

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage media in the embedded and computer system environments. In the case of reliability, however, there are many shortcomings in flash memory: potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To overcome these problems, a RAID technique borrowed from storage technology based on hard disks is employed. In the RAID technology, multi-bit burst failures in the page, block or device are easily detected and corrected so that the reliability can be significantly enhanced. However the existing RAID-5 scheme for the flash-based storage has delayed response time for parity updating. To overcome this problem, we propose a novel approach using a RAID technique in flash storage, called Flash-aware Redundancy Array. In this approach, parity updates are postponed so that they are not included in the critical path of read and write operations. Instead, they are scheduled for when the device becomes idle. For example, the proposed scheme shows a 19% improvement in the average write response time, compared to other approaches.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Soraya Zertal, "A Reliability Enhancing Mechanism for a Large Flash Embedded Satellite Storage System", Systems, 2008 ICONS 08 Third International Conference on, 2008.
 
2
Yu-Bin Chang, Li-Pin Chang, "A Self--Balancing Striping Scheme for NAND-Flash Storage Systems", Proceedings of the 2008 ACM symposium on Applied computing, 2008.
 
3
DA Patterson, G Gibson, and RH Katz, "A Case for Redundant Arrays of Inexpensive Disks(RAID)", ACM SIGMOD Record, 1988.
 
4
Disk Monitor for Windows v2.01, http://technet.microsoft.com/en-us/sysinternals/bb896646.aspx.
 
5
S.W. Lee, D.J. Park, T.S. Park, D.H. Lee, S.W. Park, and H.J. Song, "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation", ACM Transactions on Embedded Computing Systems, vol. 6, no. 3, 2007.
 
6
C.I. Park, W.M. Cheon, Y.S. Lee, M.S. Jung, W.H. Cho, and H.B. Yoon, "A Re-configurable FTL(Flash Translation Layer) Architecture for NAND Flash based Applications", 18th IEEE/IFIP International Workshop on Rapid System Prototyping, IEEE, 2007.
 
7
J.H. Kim, S. Jung, and Y.H. Song, "Cost and Performance Analysis of NAND Mapping Algorithms in Shared--bus Multi-chip Configuration", IWSSPS'08, 2008
 
8
Tae-Sun Chung, Myungho Lee, Yeonseung Ryu, and Kangsun Lee, "PORCE: An efficient power off recovery scheme for flash memory", Journal of Systems Architecture, vol. 54, no. 10, 2008.
 
9
Jesung Kim, JongMin Kim, Sam H. Noh, Sang Lyul Min, and Yookun Cho, "A Space-Efficient Flash Translation Layer for CompactFlash Systems", IEEE Transactions on Consumer Electronics, vol. 48, no. 2, 2002.
 
10
Jeong-Uk Kang, Heeseung Jo, Jin-Soo Kim, and Joonwon Lee, "A Superblock-based Flash Translation Layer for NAND Flash Memory", EMSOFT'06, ACM, 2006.
 
11
Dawoon Jung, Yoon-Hee Chae, Heeseung Jo, Jin-Soo Kim, and Joonwon Lee, "A Group-Based Wear-Leveling Algorithm for Large-Capacity Flash Memory Storage Systems", CASES'07, ACM, 2007.
 
12
Kevin M. Greenan, Ethan L. Miller, and Darrell D.E. Long, "Building Reliable NAND Flash Memory Storage Systems", International Workshop on Large-Scale NVRAM Technology, 2008.
 
13
H Jo, J Kang, S Park, J Kim, and J Lee, "FAB: Flash-Aware Buffer Management Policy for Portable Media Players", IEEE Transactions on Consumer Electronics, 2006.
 
14
C Park, P Talawar, D Won, MJ Jung, JB Im, S Kim, and Y Choi, "A High Performance Controller for NAND Flash-based Solid State Disk (NSSD)", IEEE Non-Volatile Semiconductor Memory Workshop(NVSMW), 2006.
 
15
S. Jung, J. Kim, and Y. Song, "Hierarchical Architecture of Flash-based Storage Systems for High Performance and Durability", Proceedings of the 46th annual Design Automation Conference (DAC), 2009