Scalable and retargetable simulation techniquesfor multiprocessor systems

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Scalable and retargetable simulation techniquesfor multiprocessor systems

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International Conference on Hardware Software Codesign archive
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis table of contents

Grenoble, France

SESSION: System level modeling and simulation table of contents

Pages 89-98

Year of Publication: 2009

ISBN:978-1-60558-628-1

Authors

Heekyung Kim	Seoul National University, Seoul, South Korea
Dukyoung Yun	Seoul National University, Seoul, South Korea
Soonhoi Ha	Seoul National University, Seoul, South Korea

Sponsors

ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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Downloads (6 Weeks): 17, Downloads (12 Months): 17, Citation Count: 0

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ABSTRACT

For design space exploration of embedded systems, a virtual prototyping system is commonly used to verify the expected performance as well as functionality before a hardware prototype is built. For accurate performance estimation, a virtual prototyping system is constructed by replacing real processing components with component simulators running concurrently. In such a distributed simulation system, the overhead of communication and synchronization between the component simulators increases in proportion to the number of simulators in case the lock-step synchronization is used. As a result the simulation performance is degraded significantly as the number of processors integrated in a chip increases. To overcome this problem, we propose a scalable and retargetable simulation technique that boosts the simulation performance significantly, by attaching a simulator wrapper to each component simulator. The simulator wrapper performs synchronization on behalf of the associated simulator itself between the simulators and the simulation backplane. Use of the simulator wrapper also makes the proposed simulation platform retargetable since a third-party simulator like ARMulator can be integrated into the simulation environment through a wrapper without modification. In addition, it enables parallel simulation that achieves almost linear speed-up as the number of processor cores increases in the simulation host. Through experiments with multimedia CODEC application and other applications varying the number of processor simulators from 1 to 16, it is proved that the simulation performance remains constant. And scalable performance from parallel simulation is also confirmed by experiments.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	CoWare Inc. CoWare Processor Designer. http://www.coware.com/PDF/products/ProcessorDesigner.pdf.
	2	CoWare Inc. CoWare Virtual Platform. http://www.coware.com/PDF/products/VirtualPlatform.pdf.
	3	R. Fujimoto, "Parallel discrete event simulation," Commun. ACM, vol. 33, no. 10, pp. 30--53, Oct. 1990
	4	W. Sung and S. Ha. 1998, "Efficient and flexible cosimulation environment for DSP applications", IEICE Trans. Fundam. Electron., Commun. Comput. Sci. Special Issue VLSI Design CAD Algorithms, vol. E81-A, no. 12, pp. 2605--2611, Dec. 1998.
	5	J. Jung, S. Yoo, and K. Choi, "Performance improvement of multiprocessor systems cosimulation based on SW analysis", in Proc. Des. Autom. Test Eur., Mar. 2001, pp. 749--753.
	6	M. Chung and C. Kyung, "Enhancing performance of HW/SW cosimulation and coemulation by reducing communication overhead", IEEE Trans. Comput., vol. 55, no. 2, pp. 125--136, Feb. 2006.
	7	R. Fujimoto, "Parallel discrete event simulation", Commun. ACM, vol. 33, no. 10, pp. 30--53, Oct. 1990.
	8	K. M. Chandy and J. Misra, "Asynchronous distributed simulation via a sequence of parallel computations", Commun. ACM, vol. 24, no. 11, pp. 198--206, Apr. 1981.
	9	S. Mukherjee, S. Reinhardt, B. Falsafi, M. Litzkow, S. Huss-Lederman, M. Hill, J. Larus, and D. Wood, "Fast and portable parallel architecture simulators: Wisconsin wind tunnel II", IEEE Concurrency, vol. 8, no. 4, pp. 12--20, Oct.--Dec. 2000.
	10	D. R. Jefferson, "Virtual time", ACM Trans. Program. Lang. Syst., vol. 7, no. 3, pp. 404--425, Jul. 1985.
	11	S. Yoo and K. Choi, "Optimistic distributed timed cosimulation based on thread simulation model", in Proc. Int. Workshop Hardware/Software Codes., pp. 71--75, Mar. 1998.
	12	K. Hines and G. Borriello, "Dynamic communication models in embedded system co-simulation", in Proc. Des. Autom. Conf., pp. 395--400, Jun. 1997.
	13	ARM Ltd., RealView ARMulator. Available: http://www.arm.com/products/DevTools/RealViewDevSuite.html.
	14	Y. Yi, D. Kim, S. Ha, "Fast and accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, NO. 12, December 2007.
	15	Cai, L and Gajski, D, "Transaction Level Modeling in System Level Design", Technical report. Center for Embedded Computer Systems, 2003.
	16	K. S. Perumalla, "Parallel and Distributed Simulation: Traditional Techniques and Recent Advances", in Winter Simulation Conference, Monterey, California, USA, 2006.