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Using binary translation in event driven simulation for fast and flexible MPSoC simulation
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International Conference on Hardware Software Codesign archive
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis table of contents
Grenoble, France
SESSION: System level modeling and simulation table of contents
Pages 71-80  
Year of Publication: 2009
ISBN:978-1-60558-628-1
Authors
Marius Gligor  TIMA Laboratory, CNRS/INP Grenoble/UJF, Grenoble, France
Nicolas Fournel  TIMA Laboratory, CNRS/INP Grenoble/UJF, Grenoble, France
Frédéric Pétrot  TIMA Laboratory, CNRS/INP Grenoble/UJF, Grenoble, France
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction level. To have an accurate timing behavior, we had to firstly solve timing issues in processor modeling, secondly define fast and precise cache models, and thirdly solve the synchronization issues due to the different models of computation used in the ISSes and in the rest of the system. We present an integration solution that covers these issues and detail its implementation. We have experimented our proposal using processors models provided by the QEMU framework to replace the existing ISSes and SystemC TLM as simulation environment for the whole platform. This approach proposes a range of solutions trading off simulation speed versus accuracy. The experiments show that even for the most precise configuration, the simulation speedup is still significant.


REFERENCES

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