A case study of on-chip sensor network in multiprocessor system-on-chip

ABSTRACT

Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at run time could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively detect, report, and alleviate run-time threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used and explained in our case study to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.12% performance improvement compared with the traditional stop-go method with 1.4% area overhead in an 8*8-core MPSoC in 45nm.

REFERENCES

• 1: S.R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar. An 80-tile sub-100-w teraflops processor in 65-nm cmos. IEEE Journal of Solid-State Circuits, 43(1):29--41, 2008.
• 2: Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John Brown, Matthew Mattina, Chyi--Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, and John Zook. Tile64tm processor: A 64-core soc with mesh interconnect. In Proc. Digest of Technical Papers. IEEE International Solid--State Circuits Conference ISSCC 2008, pages 88--598, 2008.
• 3: Shekhar Borkar. Thousand core chips: a technology perspective. In DAC '07: Proceedings of the 44th annual conference on Design automation, pages 746--749, New York, NY, USA, 2007. ACM.
• 4: V. Petrescu, M. Pelgrom, H. Veendrick, P. Pavithran, and J. Wieling, "Monitors for a signal integrity measurement system," Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European, pp. 122--125, Sept. 2006.
• 5: C. Poirier, R. McGowen, C. Bostak, and S. Naffziger, "Power and temperature control on a 90nm itanium-family processor," Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, pp. 304--305 Vol. 1, Feb. 2005.
• 6: R. McGowen, C. Poirier, C. Bostak, J. Ignowski, M. Millican, W. Parks, and S. Naffziger, "Power and temperature control on a 90-nm itanium family processor," Solid-State Circuits, IEEE Journal of, vol. 41, no. 1, pp. 229--237, Jan. 2006.
• 7: K. Sohn, N. Cho, H. Kim, K. Kim, H.-S. Mo, Y.-H. Suh, H.-G. Byun, and H.-J. Yoo, "An autonomous sram with on-chip sensors in an 80nm double stacked cell technology," VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on, pp. 232--235, June 2005.
• 8: K. Sohn, H.-S. Mo, Y.-H. Suh, H.-G. Byun, and H.-J. Yoo, "An autonomous sram with on-chip sensors in an 80--nm double stacked cell technology," Solid-State Circuits, IEEE Journal of, vol. 41, no. 4, pp. 823--830, April 2006.
• 9: C. Chan, Y. Chang, H. Ho, and H. Chiueh, "A thermal-aware power management soft-ip for platform-based soc designs," System-on-Chip, 2004. Proceedings. 2004 International Symposium on, pp. 181--184, Nov. 2004.
• 10: Alexander Wei Yin, Liang Guang, Pasi Liljeberg, Pekka Rantala, Ethiopia Nigussie, Jouni Isoaho, Hannu Tenhunen. Hierarchical Agent Architecture for Scalable NoC Design with Online Monitoring Services Proceedings of MICRO 41
• 11: C. Ciordas, T. Basten, A. Radulescu, K. Goossens, and J. Meerbergen. An event-based network-on-chip monitoring service. In Proc. of the 9th IEEE International High-Level Design Validation and Test Workshop, pages 149--154, 2004.
• 12: C. Ciordas, K. Goossens, A. Radulescu, and T. Basten. Noc monitoring: impact on the design flow. In Proc. IEEE International Symposium on Circuits and Systems ISCAS 2006, pages 1981--1984, 2006.
• 13: Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang, "On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise", in ISVLSI 2009, Tampa, USA, pp. 109--114.
• 14: Nanoscale Integration and Modeling (NIMO) Group, ASU. Predictive Technology Model (PTM). [Online]. Available: http://www.eas.asu.edu/~ptm/
• 15: Nangate Open Cell Library. [Online]. Available: http: //www. opencelllibrary.org
• 16: NS2, http://nsnam.isi.edu/nsnam.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.0 GENERAL

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Modeling of computer architecture

General Terms:
Design, Reliability

Keywords:
dynamic control, low-power, power grid noise, reliability, sensor network, system on chip