Take a look at the new version of this page: [ beta version ]. Tell us what you think.

ABSTRACT

Solid State Disks (SSDs) are superior to magnetic disks from a performance point of view due to the favorable features of NAND flash memory. Furthermore, thanks to improvement on flash memory density and adopting a multi-chip architecture, SSDs replace magnetic disks rapidly. Most previous studies have been conducted for enhancing the performance of SSDs, but these studies have been worked on the assumption that the operation unit of a host interface is the same as the operation unit of NAND flash memory, where it is needless to give consideration to partially-filled pages. In this paper, we analyze the overhead caused by the partially-filled pages, and propose a buffer replacement algorithm exploiting multi-chip parallelism to enhance the write performance. Our simulation results show that the proposed algorithm improves the write performance by up to 30% over existing approaches.

REFERENCES

• 1: 2Gx8 bit NAND flash memory (K9GAG08U0M). Samsung Electronics, 2006.
• 2: 2Gx8 bit NAND flash memory (K9WAG08U1A). Samsung Electronics, 2006.
• 3: SystemC. http://www.systemc.org/home, 2007.
• 4: Nitin Agrawal , Vijayan Prabhakaran , Ted Wobber , John D. Davis , Mark Manasse , Rina Panigrahy, Design tradeoffs for SSD performance, USENIX 2008 Annual Technical Conference on Annual Technical Conference, p.57-70, June 22-27, 2008, Boston, Massachusetts
• 5: Andrew Birrell , Michael Isard , Chuck Thacker , Ted Wobber, A design for high-performance flash disks, ACM SIGOPS Operating Systems Review, v.41 n.2, p.88-93, April 2007 [doi>10.1145/1243418.1243429]
• 6: T. Bisson, S. A. Brandt, and D. D. Long. A hybrid Disk-Aware Spin-Down algorithm with I/O subsystem support. In Proceedings of the 26th International Performance, Computing, and Communications Conference (IEEE IPCCC), pages 236--245, 2007.
• 7: Lukai Cai , Daniel Gajski, Transaction level modeling: an overview, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA [doi>10.1145/944645.944651]
• 8: Adrian M. Caulfield , Laura M. Grupp , Steven Swanson, Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications, Proceeding of the 14th international conference on Architectural support for programming languages and operating systems, March 07-11, 2009, Washington, DC, USA [doi>10.1145/1508244.1508270]
• 9: Li-Pin Chang , Tei-Wei Kuo, An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems, Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02), p.187, September 25-27, 2002
• 10: Peter M. Chen , Edward K. Lee , Garth A. Gibson , Randy H. Katz , David A. Patterson, RAID: high-performance, reliable secondary storage, ACM Computing Surveys (CSUR), v.26 n.2, p.145-185, June 1994 [doi>10.1145/176979.176981]
• 11: H. Jo, J. Kang, S. Park, J. Kim, and J. Lee. FAB: flash-aware buffer management policy for portable media players. IEEE Transactions on Consumer Electronics, 52(2):485--493, 2006.
• 12: Theodore Johnson , Dennis Shasha, 2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm, Proceedings of the 20th International Conference on Very Large Data Bases, p.439-450, September 12-15, 1994
• 13: Jeong-Uk Kang , Jin-Soo Kim , Chanik Park , Hyoungjun Park , Joonwon Lee, A multi-channel architecture for high-performance NAND flash-based storage system, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.9, p.644-658, September, 2007 [doi>10.1016/j.sysarc.2007.01.010]
• 14: Hyojun Kim , Seongjun Ahn, BPLRU: a buffer management scheme for improving random writes in flash storage, Proceedings of the 6th USENIX Conference on File and Storage Technologies, p.1-14, February 26-29, 2008, San Jose, California
• 15: J. Kim, D. Jung, J. Kim, and R. Huh. A methodology for extracting performance parameters in solid state disks (SSDs). In Proceedings of the 17th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (IEEE MASCOTS '09), London, United Kingdom, 2009.
• 16: J. H. Kim, S. H. Jung, and S. Y. Ho. Cost and performance analysis of NAND mapping algorithms in shared-bus multi-chip configuration. In Proceedings of the International Workshop on Software Support for Portable Storage (IWSSPS), 2008.
• 17: Tei-Wei Kuo , Jen-Wei Hsieh , Li-Pin Chang , Yuan-Hao Chang, Configurability of performance and overheads in flash management, Proceedings of the 2006 Asia and South Pacific Design Automation Conference, January 24-27, 2006, Yokohama, Japan [doi>10.1145/1118299.1118383]
• 18: S. Lee, D. Shin, and J. Kim. Buffer-Aware garbage collection for NAND flash Memory-Based storage systems. In Proceedings of the International Workshop on Software Support for Portable Storage (IWSSPS), pages 27--32, 2008.
• 19: D. R. Llanos. TPCC-UVa benchmark. http://www.infor.uva.es/~diego/tpcc-uva.html, 2006.
• 20: Nimrod Megiddo , Dharmendra S. Modha, ARC: A Self-Tuning, Low Overhead Replacement Cache, Proceedings of the 2nd USENIX Conference on File and Storage Technologies, March 31-31, 2003, San Francisco, CA
• 21: Buffer Replacement Algorithms for Multimedia Storage Systems, Proceedings of the 1996 International Conference on Multimedia Computing and Systems, p.172, June 17-23, 1996 [doi>10.1109/MMCS.1996.534971]
• 22: Ji-Yong Shin , Zeng-Lin Xia , Ning-Yi Xu , Rui Gao , Xiong-Fei Cai , Seungryoul Maeng , Feng-Hsiung Hsu, FTL design exploration in reconfigurable high-performance SSD for server applications, Proceedings of the 23rd international conference on Supercomputing, June 08-12, 2009, Yorktown Heights, NY, USA [doi>10.1145/1542275.1542324]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.3 Performance Analysis and Design Aids**
          Subjects: Simulation**

General Terms:
Algorithms, Design, Measurement, Performance

Keywords:
buffer replacement algorithm, nand flash memory, solid state disk (SSD)