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Probabilistic modeling of data cache behavior
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International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the seventh ACM international conference on Embedded software table of contents
Grenoble, France
SESSION: Time predictability and memory management table of contents
Pages 255-264  
Year of Publication: 2009
ISBN:978-1-60558-627-4
Authors
Vinayak Puranik  Indian Institute of Science, Bangalore, India
Tulika Mitra  National Univ. of Singapore, Singapore, Singapore
Y. N. Srikant  Indian Institute of Science, Bangalore, India
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we propose a formal analysis approach to estimate the expected (average) data cache access time of an application across all possible program inputs. Towards this goal, we introduce the notion of probabilistic access history that intuitively summarizes the history of data memory accesses along different program paths (to reach a particular program point) and their associated probabilities. An efficient static program analysis technique has been developed to compute the access history at all program points. We estimate the cache hit/miss probabilities and hence the expected access time of each data memory reference from the access history. Our experimental evaluation confirms the accuracy and viability of the probabilistic data cache modeling approach.


REFERENCES

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