| Clock-driven distributed real-time implementation of endochronous synchronous programs |
| Full text |
Pdf
(460 KB)
|
Source
|
International Conference on Compilers, Architecture and Synthesis for Embedded Systems
archive
Proceedings of the seventh ACM international conference on Embedded software
table of contents
Grenoble, France
SESSION: Scheduling
table of contents
Pages 147-156
Year of Publication: 2009
ISBN:978-1-60558-627-4
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 9, Downloads (12 Months): 9, Citation Count: 0
|
|
|
ABSTRACT
An important step in model-based embedded system design consists in mapping functional specifications and their tasks/operations onto execution architectures and their resources. This mapping comprises both temporal scheduling and spatial allocation aspects. Therefore, we promote an approach which starts from loosely-timed/asynchronous models and proceeds by refining them to fully synchronized ones, using so-called clock calculus techniques under the architecture constraints. In this paper we provide a modeling framework based on an intermediate representation format, called clocked graphs, for polychronous endochronous specifications, which are the ones that can be safely considered for deterministic distributed real-time implementation using static scheduling techniques. Our formalism allows the specification of both "intrinsic" correctness properties of the specification, such as causality and clock consistency, and "external" correctness properties, such as endochrony, which ensure compatibility with the desired implementation architecture, including both hardware and software aspects. Using this formalism, we define a new method for distributed real-time implementation of synchronous specification. The move from (endochronous) synchronous specification to realtime scheduled implementation is a seamless sequence of model decorations.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Nicolas Halbwachs. Synchronous Programming of Reactive Systems. Kluwer academic Publishers, 1993.
|
| |
2
|
Albert Benveniste, Paul Caspi, Stephen A. Edwards, Nicolas Halbwachs, Paul Le Guernic, and Robert de Simone. The synchronous languages 12 years later. Proceedings of the IEEE, 91(1):64--83, January 2003.
|
| |
3
|
A. Benveniste, B. Caillaud, and P. Le Guernic. Compositionality in dataflow synchronous languages: Specification and distributed code generation. Information and Computation, 163:125 -- 171, 2000.
|
| |
4
|
P. Le Guernic, J.-P. Talpin, and J.-C. Le Lann. Polychrony for system design. Journal for Circuits, Systems and Computers, April 2003. Special Issue on Application Specific Hardware Design.
|
| |
5
|
D. Potop-Butucaru, B. Caillaud, and A. Benveniste. Concurrency in synchronous systems. Formal Methods in System Design, 28(2):111--130, March 2006.
|
| |
6
|
R. Milner. Communication and Concurrency. Prentice Hall, 1989.
|
| |
7
|
G. Kahn. The semantics of a simple language for parallel programming. In J.L. Rosenfeld, editor, Information Processing '74, pages 471--475. North Holland, 1974.
|
| |
8
|
D. Potop-Butucaru, S. Edwards, and G. Berry. Compiling Esterel. Springer, 2007.
|
| |
9
|
N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud. The synchronous dataflow programming language Lustre. Proceedings of the IEEE, 79(9):1305--1320, 1991.
|
| |
10
|
S. Campbell, J.-P. Chancelier, and R. Nikoukhah. Modeling and Simulation in Scilab/Scicos. Springer, 2006.
|
| |
11
|
T. Grandpierre and Y. Sorel. From algorithm and architecture specification to automatic generation of distributed real-time executives. In Proceedings MEMOCODE, 2003.
|
| |
12
|
R. Obermeisser. Event-Triggered and Time-Triggered Control Paradigms. Springer, 2005.
|
| |
13
|
A. Benveniste, B. Caillaud, L. Carloni, P. Caspi, and A. Sangiovanni-Vincentelli. Composing heterogeneous reactive systems. ACM TECS, 7(4), 2008.
|
| |
14
|
P. Amagbegnon, L. Besnard, and P. Le Guernic. Implementation of the data-flow synchronous language signal. In Proceedings PLDI, 1995.
|
| |
15
|
A. Kountouris and C. Wolinski. Efficient scheduling of conditional behaviors for high-level synthesis. ACM Transactions on Design Automation of Electronic Systems, 7(3):380--412, July 2002.
|
| |
16
|
Z. Gu, X. He, and M. Yuan. Optimization of static task and bus access schedules for time-triggered distributed embedded systems with model-checking. In Proceedings DAC, 2007.
|
| |
17
|
W. Zheng, J. Chong, C. Pinello, S. Kanajan, and A. Sangiovanni-Vincentelli. Extensible and scalable time triggered scheduling. In Proceedings ACSD, 2005.
|
| |
18
|
P. Caspi, A. Curic, A. Maignan, C. Sofronis, S. Tripakis, and P. Niebert. From simulink to scade/lustre to tta: a layered approach for distributed embedded applications. In Proceedings LCTES, 2003.
|
| |
19
|
D. Potop-Butucaru, R. de Simone, and Y. Sorel. Necessary and sufficient conditions for deterministic desynchronization. In Proceedings EMSOFT'07, Salzburg, Austria, October 2007.
|
| |
20
|
C. L. Liu and J. Layland. Scheduling algorithms for multiprogramming in a hard real-time environment. Journal of the ACM, 20(1):46--61, January 1973.
|
|