A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution

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A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution

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ACM International Conference Proceeding Series archive
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems table of contents

Madrid, Spain

SESSION: Hardware support for real-time systems table of contents

Pages 120-129

Year of Publication: 2009

ISBN:978-1-60558-732-5

Authors

Avinash Malik	The University of Auckland, New Zealand
Zoran Salcic	The University of Auckland, New Zealand
Alain Girault	INRIA Grenoble Rhône-Alpes and Grenoble University, France
Adam Walker	The University of Auckland, New Zealand
Sung Chul Lee	The University of Auckland, New Zealand

Sponsors

: Universidad Complutense de Madrid
: ACM
Sun : Sun
: aicas GmbH

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ACM New York, NY, USA

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Downloads (6 Weeks): 21, Downloads (12 Months): 21, Citation Count: 0

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ABSTRACT

This paper presents a novel execution architecture for Globally Asynchronous Locally Synchronous (GALS) systems, in our case particularly targeting system level programming language SystemJ. SystemJ extends Java with both synchronous and asynchronous concurrency and reactivity to control program execution. The proposed architecture is based on separating the control-driven and data-driven operations onto two types of processors, respectively control and data processors, and it is aimed at complex embedded applications designed as GALS. The control processor is introduced to execute efficiently the control constructs, which implement concurrency, reactivity, and control flow in SystemJ. The data processor executes the Java data-driven transformational operations and can be any traditional processor. Control and data processors form hybrid multiprocessors, called GALS multiprocessors, which can then be easily customized for specific application and are implemented as a system on programmable chip (SoPC). Benchmarks show significant improvement in code size and execution speed of the resulting architecture over traditional processors.

REFERENCES

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	1	F. Gruian, P. Roop, Z. Salcic, and I. Radojevic, "The SystemJ approach to System-Level Design," in The 4th International Conference on Formal Methods and Models for Codesign (MEMOCODE), 2006.
	2	G. Berry, "The Semantics of Pure Esterel," Marktoberdorf Intl. Summer School on Program Design Calculi, 1993.
	3	G. Berry, "Esterel v7: From verified formal specification to efficient industrial designs," in FASE, 2005.
	4	G. Berry, S. Ramesh and R. K. Shyamsundar, "Communicating reactive processes," in Proceedings of 20^th ACM SIGPLAN-SIGACT symposium on Principles of programming language, ACM Press, NY, USA, 85--98, 1993.
	5	C. A. R. Hoare, Communicating Sequential Processes: Prentice Hall, 1985.
	6	A. Malik, Z. Salcic, and P. S. Roop, "An Efficient Execution Platform for GALS Language SystemJ," in The 13th IEEE Asia Pacific Computer Systems Architecture Conference, 2008.
	7	Z. Salcic, D. Hui, P. Roop and M. Biglari-Abhari, REMIC -- Design of a Reactive Embedded Microprocessor Core, Asia-South Pacific Design Automation Conference, Shanghai, January 2005
	8	S. Yuan, L. H. Yoong, S. Andhalam, P. Roop, and Z. Salcic, "A New Multithreaded Architecture Direct Execution Platform for Esterel," Model Driven high-level Programming of Embedded Systems SLA++P, 2008.
	9	X. Li and R. von Hanxleden, "The Kiel Esterel Processor - A Semi-Custom, Configurable Reactive Processor," Synchronous Programming - SYNCHRON'04, 2005.
	10	B. Plummer, M. Khajanchi, and S. A. Edwards, "An Esterel virtual machine for embedded systems," in International Workshop on Synchronous Languages, Applications, and Programming (SLAP), 2006.
	11	S. Edwards, "Estbench Esterel Benchmark Suite," 2006.http://www1.cs.columbia.edu/~sedwards/software.html
	12	S. Ramesh, "Communicating Reactive State Machines: Design Model and Implementation," in IFAC Workshop on Distributed Computer Control Systems, Pergamon Press, 1998.
	13	L. Lavagno and E. Sentovich, "ECL: A Specification Environment for System-Level Design," Design Automation Conference, pp. 511--516, 1999.
	14	R. Gupta, S. Pande, K. Psarris and V. Sarkar, "Compilation Techniques for Parallel Systems", Parallel Computing, 25(13): 1741--1783, 1999.
	15	Altera Corporation, "Simultaneous Multi-Mastering with Avalon Bus," April-06-2009. http://www.altera.com.cn/literature/an/an184.pdf
	16	Altera Corporation, "Nios II Processor: The World's Most Versatile Embedded Processor," 06-April-2009. http://www.altera.com/products/ip/processor/nios2/ni2-index.html
	17	A. Benveniste, P. Caspi, S Edwards, N. Halbwachs, P. L. Gnurnic and R. D. Simone, "The synchronous language twelve years later", in proceedings of IEEE, pp. 64--83, 2003.
	18	Mentor Graphics, "ModelSim SE User's Manual", June-30-2009. http://www.model.com/resources/default.asp?sendto=/support/documentation/se/pdf/modelsim_se_user.pdf
	19	I. Radojevic, Z. Salcic and P. S. Roop, "Modelling heterogeneous embedded systems using SystemC and Esterel: A comparative study", in IEEE Design and Test of Computers, Vol. 23(5) pp. 348--358, 2006.