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ABSTRACT

Energy efficiency is key in embedded systems design. Besides the CPU, DRAM has been identified as one of the main contributors to energy consumption in such devices. Modern DRAMs also offer low power states to adapt to varying workload and increase energy efficency. A number of studies have investigated different DRAM energy management strategies and propose a very aggressive use of low power states. The weakness of all of these studies is the underlying power model which does not account for transition overheads, and the lack of experimental evidence. We implemented a hardware controlled DRAM power management unit in an XScale based evaluation board and accurately measured the effects on runtime and power consumption. We observed that aggressive power management will even increase the average power consumption, due to the fact that all JEDEC compatible DRAMs execute a refresh when entering the power saving SREF-mode. This is not reflected in current, published power models. Thus, they dramatically overestimate the effectiveness of using low power states. We developed a new model for accurate timing and energy simulation of the observed effects. This model is integrated into the XEEMU XScale Energy Emulator.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS

General Terms:
Measurement, Performance

Keywords:
SDRAM, measurement, modelling, power management