A packet-switched network architecture for reconfigurable computing

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A packet-switched network architecture for reconfigurable computing

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ACM Transactions on Embedded Computing Systems (TECS) archive
Volume 9 , Issue 1 (October 2009) table of contents

Article No. 7

Year of Publication: 2009

ISSN:1539-9087

Authors

Scott Lloyd	Brigham Young University, Provo, UT
Quinn Snell	Brigham Young University, Provo, UT

Publisher

ACM New York, NY, USA

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ABSTRACT

A packet-switched network architecture named Qnet and programming interface is presented that simplifies the integration of reconfigurable computing modules within a Field-Programmable Gate Array (FPGA). Qnet provides an abstraction layer to the designer of FPGA accelerator modules that hides the complexities of the system, while supporting a high degree of parallelism and performance. The architecture facilitates system design with pluggable, reusable modules. A network protocol is described that supports a three-party communication scheme between an initiator, a sender and a receiver. This protocol allows a master device to manage the state of other devices and the data flow within the system. An example using a high-level language is given. The Qnet architecture opens the computational power of FPGAs to computer scientists and software developers.

REFERENCES

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