A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM

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A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design table of contents

San Fancisco, CA, USA

SESSION: Design contest table of contents

Pages: 119-120

Year of Publication: 2009

ISBN:978-1-60558-684-7

Authors

Ki Chul Chun	University of Minnesota, Minneapolis, MN, USA
Pulkit Jain	University of Minnesota, Minneapolis, MN, USA
Chris H. Kim	University of Minnesota, Minneapolis, MN, USA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

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ABSTRACT

A logic-compatible low power eDRAM is demonstrated in 65nm CMOS achieving a retention time of 1.25msec and a static power dissipation of 91.3µW/Mb at 0.9V, 85ºC. A boosted 3T gain cell enhances data retention time and read speed. A regulated bit-line write scheme and a read reference bias generator mitigate write disturbance issues and improve tolerance to PVT variations.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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