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ABSTRACT
Image rendering is the performance bottleneck in many computer-graphics systems today because of its computation-intensive nature. Described here is a one-chip VLSI implementation of a shaded-polygon renderer which provides an affordable solution to the bottleneck. The chip takes advantage of a unique extension to Bresenham's vector drawing algorithm [1] to interpolate four axes (for Red, Green, Blue and Z) across a polygon, in addition to the X and Y values. Its inherent accuracy and ease of high-speed hardware implementation distinguish this new algorithm from interpolation with incrementing fractions (DDA).This chip was designed as part of a workstation primarily for mechanical engineering CAD applications. The pipelining and internal bandwidth possible on the chip allows rendering speeds of over twelve-thousand, 1000-pixel, shaded polygons per second, suitable for interactive manipulation of solids. Described in this paper is the derivation of the new algorithm and its implementation in a pipelined, polygon-rendering chip.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Hiroyuki Sato , Mitsuo Ishii , Keiji Sato , Morio Ikesaka , Hiroaki Ishihata , Masanori Kakimoto , Katsuhiko Hirota , Kouichi Inoue, Fast image generation of construcitve solid geometry using a cellular array processor, ACM SIGGRAPH Computer Graphics, v.19 n.3, p.95-102, Jul. 1985
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CITED BY 19
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Sylvain Karpf , Christophe Chaillou , Eric Nyiri , Michel Meriaux, Real-time display of quadric on the I.M.O.G.E.N.E. machine, Proceedings of the first ACM symposium on Solid modeling foundations and CAD/CAM applications, p.269-277, June 05-07, 1991, Austin, Texas, United States
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Nader Gharachorloo , Satish Gupta , Erden Hokenek , Peruvemba Balasubramanian , Bill Bogholtz , Christian Mathieu , Christos Zoulas, Subanosecond pixel rendering with million transistor chips, ACM SIGGRAPH Computer Graphics, v.22 n.4, p.41-49, Aug. 1988
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Henry Fuchs , John Poulton , John Eyles , Trey Greer , Jack Goldfeather , David Ellsworth , Steve Molnar , Greg Turk , Brice Tebbs , Laura Israel, Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories, ACM SIGGRAPH Computer Graphics, v.23 n.3, p.79-88, July 1989
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Masatoshi Kameyama , Yoshiyuki Kato , Hitoshi Fujimoto , Hiroyasu Negishi , Yukio Kodama , Yoshitsugu Inoue , Hiroyuki Kawai, 3D graphics LSI core for mobile phone "Z3D", Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware, July 26-27, 2003, San Diego, California
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